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I am a begginer in the field of microcomputers and their architecture and recently I got an assignment with the following instructions:

With the use of the mapping table find out which adresses in IC2, IC3 and IC4 circuits occupy the system address space. In case of incomplete decoder list all address blocks in which the circuits are mirrored.

If I understood corectly, the system data bus has 8 bits - AD [0..7], and all of the mentioned ICs (IC2-4) has 8 bits on local data bus. If I'm correct, that means I can use 1:1 mapping. I made a table where I mapped the IC2 and IC3. On these two ICs the Chip Select pins are A15, so I could use logic 0 and 1 for selecting them.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 System Address Bus
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IC2 Local Address Bus
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <0000H
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFF>
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IC3 Local Address Bus
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <8000H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFF>

I am pretty sure that I missed something, because now I can not map the IC4. Also there are the WR#, RD# and PSEN# signals and 3 NAND gates below the 3 ICS, which have something to do with the IC4, but I do not know what.

Can someone please help to navigate me, what should I do?

Here is the scheme and the mentioned ICs are in the yellow-red square in the right part of the picture.

Scheme

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    \$\begingroup\$ Just write out truth tables for the logic gates to see which memory chip is reacting to which signals. It also looks like you assume the 8051 has a single 64kB memory space but it doesn't, so I recommend reading how 8051 external buses work. \$\endgroup\$
    – Justme
    Nov 12 '21 at 9:54
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    \$\begingroup\$ This map table should include all signals RD, WR, PSEN, ALE, ... and not only A15..A0. There is 3 IC which have 32k x 8 memory. Where are they ? \$\endgroup\$
    – Antonio51
    Nov 12 '21 at 11:05
  • \$\begingroup\$ Something as this ... i.stack.imgur.com/71kdu.png \$\endgroup\$
    – Antonio51
    Nov 12 '21 at 12:43
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    \$\begingroup\$ These are all good hints at solving your homework problem. I would add that you review briefly the AT89S52 chip datasheet (can find one here: rocelec.widen.net/view/pdf/xzrqsynxrv/…) and review the descriptions of those pins involved (such as RD#, WR#, and PSEN#) with the memory chips (IC2, IC3, IC4). Next, do the same for the memory chips and pins WE\, OE\, and CS\. This should help you construct the memory map table. \$\endgroup\$ Nov 12 '21 at 16:06
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    \$\begingroup\$ Read for example, paragraph 6, page 10, about memory organization for AT89S52 (above link). You can see that some instruction knows what data to use and where ... See also this : electronicshub.org/8051-microcontroller-memory-organization annamalaiuniversity.ac.in/studport/download/engg/csd/resources/… \$\endgroup\$
    – Antonio51
    Nov 12 '21 at 17:17

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