I have a piece of code in Verilog which needs to assign the value of shift register to an output register when the shifting has finished, and I want to reset the value of the shift register in the same clock cycle. Like the following:
[shift register processing during several clock cycles...] output_buffer <= shift_register; shift_register <= 0;
I'm aware of non blocking assignments are done in parallel, meaning that they are done 'at the same time'. Having that on mind, the above piece of code should have an undefined behaviour: if both assignments happen 'in parallel', because in the end nothing can happen literally at the same time.
I have tried this on a simulator and it works as I expect, that is,
output_buffer gets the shift reg. value and the latter is reset. However, in general, is it safe to execute this on a real FPGA?