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I'm using the ADC on pin 14, PA2, on the LQFP64 STM32G474CB (datasheet). What is the ADC input range for this pin? Here is my assessment let me know if my understanding is incorrect:

Table 12. Pin Definitions shows this pin's I/O structure as FT_a as shown below:

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The FT_a type is 5V tolerant I/O with an analog switch function supplied by Vdda according to Table 11. Legend/abbreviations used in the pinout table shown below:

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The Absolute maximum rating for FT_xxx pin is min(Vdd, Vdda) + 4 according to Table 14 Voltage characteristics shown below:

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Finally, the Vdda analog supply voltage for the ADC is listed as 3.6V max according to Table 17. General operating conditions shown below:

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So with all that said, PA2 is tolerant to an absolute maximum voltage of Vdd + 4 (assuming Vdd is 3.3V) so 7.3V but typically 5V. However, when using this pin as an ADC it would saturate the ADC reading if the input voltage exceeded 3.6V due to 3.6V being Vdda's max. The PA2 wouldn't be damaged unless this pin unless it was exposed to Vdd+4V or higher. I reviewed this post and it seems to be in alignment but I just want to make sure. STM32 ADC Input voltage

Is my assessment correct?

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However, when using this pin as an ADC it would saturate the ADC reading if the input voltage exceeded 3.6V due to 3.6V being Vdda's max.

The ADC would saturate at actual VREF+. The maximum rating of VDDA has nothing to do with saturation.

PA2 is tolerant to an absolute maximum voltage of Vdd + 4 (assuming Vdd is 3.3V) so 7.3V but typically 5V.

Since the formula has min(VDD,VDDA) if your VDDA is less than VDD then it will define the maximum, not VDD. Other than that the assumption seems to be correct. Having said that, running MCU at absolute maximum ratings is a recipe for premature death, as even small supply deviation can push it over the limit.

You also missed one more condition, the maximum allowed difference between VREF+ and VDDA, which is only 0.4V. This means that even if you push VDDA to its 3.6V maximum, you can use at most 4V as VREF+. And since that is where ADC will saturate, applying more than 4V to analog inputs does not make any sense, regardless of whether or not they can survive it.

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  • \$\begingroup\$ Right, I am getting Vdda and VREF+ conflated with each other. Also, I have no intention of running anywhere near the absolute max level, I was only trying to ensure I understand the parameters I am working within. Thank you for pointing out the min(Vdda, Vdd) and the VREF+ VDDA delta I did not catch those details. \$\endgroup\$
    – Tim51
    Nov 12, 2021 at 20:22

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