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Say we slow down time to a crawl, and turn on a power source connected to a unity gain buffer. Initially, the non-inverting input receives the signal and the inverting input receives nothing, so the output is indeed the signal. Right after, the signal is fed back to the inverting input. Would that not mean that the output should then be 0, since the differential amplifier would output the difference between the signal and itself?

Schematic of unity gain buffer

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  • \$\begingroup\$ Right. But after a moment the signal will increase to some non-zero value, and the difference won't be zero anymore \$\endgroup\$
    – Eugene Sh.
    Commented Nov 12, 2021 at 20:58
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    \$\begingroup\$ The diff amp outputs 10^6 to 10^7 times the difference between the signal and itself, it's a very high gain amplifier, so the difference between the inputs is driven to something very small. It's only the closed loop gain that's 1. \$\endgroup\$
    – Neil_UK
    Commented Nov 12, 2021 at 21:03
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    \$\begingroup\$ If the inverting input receives nothing then, if the op-amp has infinite output slew rate capability, the output would be put hard against a supply rail. Some short time later, negative feedback would make the two inputs virtually the same amplitude. \$\endgroup\$
    – Andy aka
    Commented Nov 12, 2021 at 21:03
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    \$\begingroup\$ Schematic? I assume that you mean a typical op-amp circuit configured as a unity-gain buffer, but that's an assumption. \$\endgroup\$
    – TimWescott
    Commented Nov 12, 2021 at 21:25
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    \$\begingroup\$ It can swing and oscillate just as you say but, opamps are designed not to produce too much of a counter reaction and things settle down fairly quickly @DavidCian \$\endgroup\$
    – Andy aka
    Commented Nov 13, 2021 at 0:16

6 Answers 6

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You've applied the non-idealities of the op amp inconsistently, and have reached a false contradiction. In particular, you've assumed that the op amp has infinite open-loop gain when you concluded that output = input, but then added the non-ideality of finite open-loop gain (meaning that diff. input = 0 implies output = 0) halfway through the problem.

If you accept that the open-loop gain is a finite value \$A_0\$, then it can be shown that your overall closed-loop gain of the unity-gain amplifier is \$\frac{A_0}{1+A_0}\$. This is of course consistent: if you apply 1 V to the non-inverting input, then your output is \$\frac{A_0}{1+A_0}\$, the difference in the inputs is \$\frac{1}{1+A_0}\$, and multiplying that by \$A_0\$ matches up.

If you instead accept that the open-loop gain is infinite, then you can only reach the conclusion that in feedback, the two inputs have equal voltage and hence the output must equal the input.

However, let's actually take a really simple op amp model, and slow down time as you asked. I'll demonstrate that this steady-state gain isn't all we see, and there are actually some pretty cool slew-rate behaviors. This should cover this clarification comment of yours:

If I get this right, the inverting input gets nothing, the difference between the two is then just the initial signal, which swings to say the positive supply rail if the initial signal was positive. But then, the signal minus the feedback would be negative and get pushed to the negative supply rail, right? Doesn't this just lead to infinite oscillations?

I'll take a little five-transistor1, single-stage op amp (using TSMC's 180nm mixed-signal process, and not optimized for slew rate). Every op amp will be different in what it does. Some may undershoot. Some may overshoot like mine. Some may swing around the output for a few oscillations if they're only barely stable at unity gain.

enter image description here

The principle of this circuit is as follows. It's not representative of every op amp, but knowing the theory behind the example is important toward understanding the slew rate remarks I'll make soon.

  1. NMOS_IDC_IN and NMOS_IDC_OUT form a current mirror which delivers a constant current to the differential pair.
  2. NMOS_IN_P and NMOS_IN_N form a differential pair. When VIN_P is above VIN_N, more current is sunk by NMOS_IN_P from the left branch and less is sunk by NMOS_IN_N from the right branch. When the two are equal, the currents are equal.
  3. When less current is sunk from the right branch by NMOS_IN_N, the output directly rises.
  4. When more current is sent via the left branch, the PMOS_LOAD_P and PMOS_LOAD_N pair copy the current back down the right branch.
  5. The resulting small signal currents are sent into the load.

The gist here is that this amplifier operates in a differential-to-single-ended transconductance mode. We deal in differences of voltages for the input, and we send current in or out of the output pin.

enter image description here

Here's a simple testbench:

enter image description here

At the start, our op amp is already showing its non-ideal, finite gain. We put in 400 mV, we got out 407 mV.

Next, I'm going to abruptly increase the input voltage of the unity-gain buffer from 0.4 V to 1.4 V, while looking at three things:

  • The input voltage (red, dotted)
  • The output voltage (yellow)
  • The internal gate voltage that's responsible for delivering current into the output (green), which I'll call PGATE. The lower this voltage goes, the more current we can deliver into the output.

Over the 100 ps that the input is swinging, nothing happens. The amp is just too sluggish to respond much. We get 65 mV of output swing for 1000 mV of input swing. It's mostly the input spike directly getting conducted through parasitic capacitances into the output.

enter image description here

Now let's look at the whole output slope:

enter image description here

NMOS_IN_P turns on more strongly; It's sinking a fair amount of current but it can only sink as much current as the current mirror sinks (50 uA). As it turns on, we see PGATE drop and the upper current mirror activates to send more current into the load.

At the same time, NMOS_IN_N cuts off.

We're now slewing the output as fast as this amplifier possibly could - the left branch (NMOS_IN_P) is taking every ounce of bias current it can, and sending a copy of that bias current into the load since the upper mirror is copying it. At the same time, NMOS_IN_N is cut off, taking no current. No matter how hard we drive VIN_P, it can't go any faster (i.e. we are thinking about a constant slew rate, not a gain as a function of the input voltage). The left branch can't carry more than the total bias current, and the right branch can't carry less than no current.

As we reach the point where VIN = VOUT, things are still not quite in balance. NMOS_IN_N is completely shut off and will be sluggish to turn on. Likewise, the upper current mirror is driving a large amount of current, and turning it off will take a while, so the amplifier overshoots. As the current mirror dials its output back to the steady state bias current, and as NMOS_IN_N turns back on, the output settles to its final value, 1.3973 V (a tad shy of 1.4 V).

1 Six transistors, actually. Only five are part of the op amp core; the sixth establishes a bias voltage as the reference side of the tail current mirror.

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  • \$\begingroup\$ Tiny nitpick on an overall excellent answer: you call it a 5-transistor op amp, but I count six transistors. I guess you're not counting the current mirror's reference transistor? \$\endgroup\$
    – Hearth
    Commented Nov 13, 2021 at 19:27
  • \$\begingroup\$ @Hearth That's correct, we didn't count that one (in practice it could also be shared amongst multiple op amps that are close enough on-die to have good-enough matching). My instructor and text both used that term, so the name stuck. \$\endgroup\$
    – nanofarad
    Commented Nov 13, 2021 at 23:59
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The opamp will output (a very high open-loop gain) x (Vp - Vm).

With feedback, a simplified view is:

  • the opamp will drive its output to whatever is necessary to make its inputs equal.

Like all simplifications, there's some conditions. The feedback must be not be positive feedback, where an increase in output leads to an increase in input. And it is limited by the opamp supply voltages. But when you're looking at a typical and functioning opamp circuit, it helps you see what's going on.

For example, let's consider the below circuit with +30 V and -30 V supply rails and R1=R2, say 10K each. That's a nice easy halving potential divider. Vp=0 V anyway, so let's change VIN from 0 V to 5 V.

enter image description here

(huge gain) x (0 - 5) is some huge negative number so the opamp output (VOUT) goes hurtling towards a dead stop at the -30 V supply rail. It takes time to get there, as it has a maximum slew rate. On the way, it goes to -5 V. This makes Vm to be halfway between 5 V and -5 V, which is 0 V. The inputs are equal.

If the output continued towards the -30 V rail, for argument's sake reaching reaching -6 V, VIN will be halfway between 5 V and -6 V, so VIN is -0.5 V.

Now VOUT will be (huge gain) x (0 - -0.5) which is some huge positive number. So the opamp output would go hurtling towards the positive rail, again at a limited speed because of its slew rate.

That illustrates how the opamp in fact balances its output to keep its inputs equal. In reality, there's no bouncing past the threshold and going back, it's a smoother action than that in the shown circuit. I could remove the simplicity and detail other limitations but let's not muddy the water of this simplified view while you're getting to understand the basics.

So...

With a unity gain opamp configured as a buffer like you have, the output must drive the same voltage onto Vm as was input on Vp.

Hence the output voltage is the input voltage, ignoring errors introduced by the opamp's imperfections.

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  • \$\begingroup\$ This is exactly the kind of answer I was looking for, this is very clear, especially the limited slew rate part. There is only one small thing which bothers me, which is that (as per the schematic I added to my question) there aren't either of the two resistances in your answer (which is I believe a schematic for an inverting amplifier circuit). I'm having trouble transposing your answer for this case... \$\endgroup\$
    – David Cian
    Commented Nov 13, 2021 at 11:58
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    \$\begingroup\$ @DavidCian, glad to hear it helps. Does the final paragraph not explain your circuit then? \$\endgroup\$
    – TonyM
    Commented Nov 13, 2021 at 13:00
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    \$\begingroup\$ Never mind, your final paragraph makes the connection perfectly, this is a great answer, thank you! All clear now! \$\endgroup\$
    – David Cian
    Commented Nov 13, 2021 at 13:07
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Right after, the signal is fed back to the inverting input. Would that not mean that the output should then be 0, since the differential amplifier would output the difference between the signal and itself?

It would if the output were exactly the same as the input. However, the output will differ by a very small amount, called the error voltage, and that small amount gets amplified to create the output. (The error voltage is the voltage difference between the inverting and non-inverting input pins.)

Here is a circuit which shows this:

schematic

simulate this circuit – Schematic created using CircuitLab

The simulation I ran used a sine wave, which allows another point to be made, which is that the error voltage is out of phase with the input and the output. (Typically, it is close to 90 degrees out of phase for most of the useable frequencies for an op-amp). This is because an op-amp will typically have an internal compensation network that a) causes the open loop gain to fall off at approximately 6 dB / octave (20 dB / decade) and b) causes a phase shift between the error voltage and the output voltage.

enter image description here

The error voltage in this simulation has been multiplied by 100,000 to make it visible when compared to the input/output voltages.

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Assuming you mean a typical op-amp circuit in unity gain.

There's different levels of accuracy that you can impose on the model, leading to different answers.

In the easiest model, the op-amp has magically infinite gain, responds magically (infinitely) fast, and the circuit is just magically stable. In this case, when the \$V_{in}\$ jumps, \$V_{out}\$ jumps to match, because -- magic.

In the next-most-easy model, the op-amp has magically infinite gain, but it responds as an integrator -- the output is equal to the integral of the difference between input voltages. In this case, the circuit requires no magic to be stable. This model is actually pretty good for predicting the response of most circuits when the all-magic model doesn't work.

  1. \$V_{in}\$ jumps, generating a difference between \$V_+\$ and \$V_-\$.
  2. \$V_{out}\$ starts rising, at a rate equal to some constant \$A\$ times \$V_+ - V_-\$.
    • More formally, \$\frac{d}{dt} V_{out} = A\left(V_+ - V_-\right)\$. If you've gotten that far in your studies, this is an easy differential equation to solve, and you find out that \$V_{out}\$ settles to \$V_{in}\$. It must, because that's where \$\frac{d}{dt}V_{out} = 0\$

    • And conveniently, \$A\$ is equal to the gain-bandwidth product of the op-amp, in radians per second. So you can just look it up in the datasheet.

There's harder models yet, but how far you need to go depends on what part of the answer you need to look for, and what sort of op-amp you're using. A limited list of things that start affecting your answer are:

  • An op-amp that uses bipolar transistors may leak current between the inputs when the voltage difference is large (this'll be in the datasheet, as some sort of maximum differential voltage).
  • Nearly every op-amp has a finite gain, usually in the \$10^6\$ to \$10^7\$ range (but I've seen as low as an eyebrow-raising 100).
  • All op-amps have some sort of a nonlinear slew limitation, beyond the simplistic differential equation.

schematic

simulate this circuit – Schematic created using CircuitLab

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To be honest you're making quite a few fundamental errors in your understanding of the way it operates even at ideal conditions. I'm not going to look at this from the real perspective and stick to the "ideal" theoretical perspective, as the other has already been answered quite elegantly by others.

One, you're assuming instantaneous reaction to any change to the terminal voltages, which in terms of math means that Δt=0 between any action and reaction. There's a fundamental issue with that... since any change is met with a corresponding change at Δt=0 there's an infinite number of operations that can occur at any single point in the time domain. So the three points (start, charge, discharge) you're considering in your analysis are actually at the same point in time. So in this case it is both Vin and Gnd at the same point in time.

Two, you're only accounting for instantaneous charging, and not the equivalent instantaneous discharge characteristics that would also take place into Gnd. Granted your circuit doesn't have a Gnd node.. but without it, using only the schematic given, we charge the Vout node to Vin and then shut the Op Amp OFF... which means Vout = Vin anyway, since there's no place for that energy to go and will end up having a homogenous charge distribution along that node. Our answer is still Vin though.

Next, lets introduce a Gnd node at the end of Vout. So in your example, yes, you would have instantaneous charge from the Op Amp up to Vin, but you also have that energy instantaneously discharge into Gnd, since if one is true the other must also be in fact true. So really while you have a Δt=0 for reaction speed, you also have a Δt=0 for the reaction to Gnd. This means it both charges and then instantly discharges to Gnd, so you're looking at the charge/discharge line and thinking it's two points in time Δt≠0... However, this is an untrue statement. It both charges and discharges at the same point in time.

This means that while, yes, the Vout nodal voltage would go to Vin and down to Gnd, it didn't go to Gnd because the two nodes of the Op Amp were equivalent, it went to Gnd because the nodal voltage is already Gnd and current would flow from + to - which means no current enters the V- node and thus you never actually distribute any charge to the V- pin at Vin level and thus the Op Amp stays in it's ON state, which will pump out... Vin.

I hope that provides some clarity as to the assumptions you made, but didn't translate to everything in the system. You essentially asked, what happens if we allow instantaneous charging by the Op Amp, but didn't not apply those same ideal characteristics to the Gnd.

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A universal method for understanding op-amp circuits with negative feedback is:

In the first moments, when the input voltage changes, think of op-amp not as a proportional device (amplifier) ​​but as an integrator. Then, this "integrator" gradually becomes an amplifier and reaches the point of equilibrium.

You can even think of an op-amp as a "dynamic amplifier" that smoothly changes its gain from zero (at the beginning of the change) to a maximum (at the end of the change) when it reaches equilibrium...

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