I don't have much experience with PCB design, but I am currently designing one to connect together several components for a work project. One of these components is connecting an external trigger signal to an input pin on a Neso Artix 7 FPGA board. The device that generates the trigger may vary (e.g. an analog waveform generator) and the voltage of the trigger signal can therefore vary as well (although it will probably be below a maximum of 15 V or so). The trigger signal will contain pulses or a square wave at a rate of several kHz.
The FGPA operates at a logic level of 3.3 V so I think it would be a good idea to limit the voltage over the FGPA pin, in case a higher voltage trigger signal is connected. I've read about several approaches, such as an op-amp voltage clamp or a Zener diode shunt regulator. Because the trigger will likely have very high slew rates, I'm afraid that the op-amp clamp might not reach the clamping voltage quickly enough, thus possibly still damaging the FPGA.
For the Zener diode approach, I've come up with the schematic below. However, I have read that there are some drawbacks to using Zener diodes, mainly concerning power dissipation.
In this scenario, what would be the best method for protecting the FPGA from voltages higher than 3.3 V? In the case that that would be the Zener diode shunt regulator, do I need to take extra measures with regard to the power dissipation, or would the resistor in the circuit below be enough?
For the output signal, minimal time delay and slew rate are essential, since the device triggers on an edge.
Many thanks in advance!