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I don't have much experience with PCB design, but I am currently designing one to connect together several components for a work project. One of these components is connecting an external trigger signal to an input pin on a Neso Artix 7 FPGA board. The device that generates the trigger may vary (e.g. an analog waveform generator) and the voltage of the trigger signal can therefore vary as well (although it will probably be below a maximum of 15 V or so). The trigger signal will contain pulses or a square wave at a rate of several kHz.

The FGPA operates at a logic level of 3.3 V so I think it would be a good idea to limit the voltage over the FGPA pin, in case a higher voltage trigger signal is connected. I've read about several approaches, such as an op-amp voltage clamp or a Zener diode shunt regulator. Because the trigger will likely have very high slew rates, I'm afraid that the op-amp clamp might not reach the clamping voltage quickly enough, thus possibly still damaging the FPGA.

For the Zener diode approach, I've come up with the schematic below. However, I have read that there are some drawbacks to using Zener diodes, mainly concerning power dissipation.

My question
In this scenario, what would be the best method for protecting the FPGA from voltages higher than 3.3 V? In the case that that would be the Zener diode shunt regulator, do I need to take extra measures with regard to the power dissipation, or would the resistor in the circuit below be enough?

For the output signal, minimal time delay and slew rate are essential, since the device triggers on an edge.

Many thanks in advance!

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ what are the frequencies/bandwidths at which you need signals to pass to your FPGA? The faster the signals, the harder they are to protect against overvoltages. \$\endgroup\$ Nov 14, 2021 at 13:27
  • \$\begingroup\$ @MarcusMüller the bandwidth of the trigger signal will probably be around 15 MHz. I didn't yet take this into account, but as bobflux pointed out, the Zener diode is probably not the best solution in this case. \$\endgroup\$ Nov 14, 2021 at 15:29
  • \$\begingroup\$ Does it trigger on a rising edge or a falling edge? If you can live with a design that has a fast response to rising edges but a slow response to falling ones than a transistor switch with pull-up may be a good solution. \$\endgroup\$ Nov 15, 2021 at 0:04
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    \$\begingroup\$ Would a high speed optocoupler be a suitable alternative? If a few ns of trigger delay is acceptable, then there's a few options. \$\endgroup\$ Nov 15, 2021 at 17:50
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    \$\begingroup\$ @hexahedronest the main drawback I can think of is footprint, if your pcb needs to be compact then a simple zener circuit may be smaller. There might be some issues but you'd have to speak to someone who knows more about them. \$\endgroup\$ Nov 16, 2021 at 11:57

2 Answers 2

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It depends on how fast you want it...

enter image description here

Zener diodes have pretty high capacitance, so you'll need a low value series resistor, which means it will draw a lot of current from the signal source. With your 100R value, a 15V source would have to provide (15-3.3)/100 = 117mA current, and the resistor would burn 1.3W. Both are inconvenient.

If the signal is slow you can use a higher resistor, for example 3k3, which will make dissipation negligible but combined with Zener diode capacitance it will lowpass your signal at a few hundred kHz and introduce some phase shift too.

So you can use a pair of low capacitance diodes, there are many choices of dual diodes in SOT-23 available. You can use Schottky diode for a lower threshold voltage:

enter image description here

The first resistor limits current from the source, diodes limit voltage between -0.6V and 0.6V above VCC (or 0.3-0.4V if you use Schottky diodes). Since it will still go below GND and above VCC, the second resistor limits current into the FPGA protection diodes in case they conduct before the dual diode.

However it requires VCC to be able to sink some current, which won't happen if the loads are pretty low, for example a microcontroller in sleep mode. If the load on 3V3 is an FPGA, it'll draw enough power to sink the input current, so that's fine.

I've used this too:

enter image description here

The transistor and diodes make a shunt regulator at about 2.1V, the top diode and transistor add 0.6V twice, that will clip input voltage at 3V3. It follows the power supply, so it will behave correctly if the device is unpowered too.

You could also use a unidirectional TVS diode instead. It works like a Zener diode, with much lower capacitance at the cost of much lower accuracy. "Unidirectional" means it works like a normal diode in reverse, which is what you want since you're not interested in negative voltages.

So say you get a TVS diode specified for minimum 3V3, it will sink almost zero current at 3V3, but it will clamp the voltage so somewhere around 4.5-5V. So you still need a protection resistor to the FPGA pin, but it will conduct much less current than if the input was 15V and not limited to 5V.

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  • \$\begingroup\$ Thanks for your very detailed answer! I didn't realize that the Zener diode capacity was that high. In combination with the higher series resistor it would have definitely filtered out the fast edges in the trigger signal (which will have a bandwidth of ~15 MHz). Since the FPGA should essentially always be powered if a trigger source is connected, I think I will try implementing the dual diode solution, but I'll definitely look into your more elaborate suggestion for extra protection. Thanks! \$\endgroup\$ Nov 14, 2021 at 15:27
  • \$\begingroup\$ Dual diode is usually fine. You can put a decoupling cap between VCC and GND very close to sink ESD spikes to ground, and a few pF cap across the input resistor to compensate for diode capacitance. \$\endgroup\$
    – bobflux
    Nov 14, 2021 at 22:09
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Any accountable credits of this answer have to go to @bobflux . bobflux's answer points out all the aspects to be considered. I just would add a variation of bobblux's.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ +1 for the cap to make it faster \$\endgroup\$
    – bobflux
    Nov 14, 2021 at 15:33
  • \$\begingroup\$ Thanks for your suggestion! What would be the advantage of using a Schmitt trigger here in addition to the dual diode clamp before the signal is fed into the FPGA? \$\endgroup\$ Nov 14, 2021 at 15:35
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    \$\begingroup\$ @hexahedronest, Two conditions, for the advantage of Schmitt trigger; 1) You might be concerned of the FPGA input, voltage & impedance spec to the signal appearing on the pin (bobflux's second circuitry). 2) Along with that, added input conditioning components (R, C, & parasitic) may distort the signal. \$\endgroup\$
    – jay
    Nov 14, 2021 at 16:24
  • \$\begingroup\$ @hexahedronest you may consider a shunt (R and or C) along the D2, though all depends on your detailed design, and the nature of the input signal. \$\endgroup\$
    – jay
    Nov 14, 2021 at 16:36
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    \$\begingroup\$ I often put a "sacrificial" buffer for any external signals going into an FPGA that may go wildly out of range. If something goes terribly wrong the cheap/easy to replace device suffers rather than the large/difficult to replace FPGA. Also don't forget that small SMT resistors are only rated for 50V or so, you may need to put more than one in series. \$\endgroup\$ Nov 14, 2021 at 18:12

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