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I've designed and built an inverting buck-boost converter, but there is a persistent ripple that occurs on both the input and output voltage waveforms, regardless of input and output capacitor sizing. I initially thought this was due to capacitor ESR, but reducing this by placing capacitors in parallel only slightly helps reduce ripple. I've tried with up to 2200uF capacitors at 100kHz. Any ideas on how to rectify this? I'm testing at a lower current than designed, so could maybe DCM be causing the voltage ripple?

Image 1 below is the converter output voltage at fsw=100kHz.

Channel 1 of image 2 is the drain-source voltage over the switch and channel 2 is the source voltage, which is an ideal DC when the converter is not connected

Output Voltage

Drain-source and input voltage

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  • \$\begingroup\$ Before answering, could you please markup in one of the images, to what you are referring as "ripple". I see about 100 mV ripple in Image 1, which doesn't sound unusual. \$\endgroup\$
    – tobalt
    Nov 15, 2021 at 13:03
  • \$\begingroup\$ By ripple I mean the voltage spikes/peaks every 10us. The magnitude is about one volt. \$\endgroup\$
    – user300036
    Nov 15, 2021 at 14:03
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    \$\begingroup\$ Ok, this is not usually called "ripple" in SMPS jargon but "switch noise". How do you probe ? Do you have low inductance differential probes or a "pigtail" ground clamp ? Without proper probing, you could easily pick up some common-mode noise that is radiated away. Please update your question with more detail on how you probe and on your layout. If it is real, it is quite difficult to fix by adding some components. The best way is good layout around the switch node. \$\endgroup\$
    – tobalt
    Nov 15, 2021 at 14:09

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An issue that often comes up when probing switch mode supplies is coupling from the inductor to the probe, especially if the inductor is unshielded. Try probing on the opposite side of the board or locally at the load.

Also, the local currents through the output bypass cap can be large. Check your layout (especially grounding) against the chipmaker’s recommendation.

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