How is clock gating physically achieved inside an FPGA or ASIC?

Question

It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or disabled?

Answer 1

Is it a bad idea to gate clocks? It depends.

In the ASIC there’s well-understood timing for clock paths, so it’s reasonable to instance a standard cell on the clock tree to gate a sub-region’s clock. On ASIC then, not only is clock gating not ‘a bad idea’, it’s widely used as a means to save power.

Not so much with the FPGA. In fact, it’s never a good idea to create gated clocks directly out of FPGA fabric logic; the synthesis tools will warn you about it if not outright forbid it. Why? The resulting inserted skew becomes impossible to manage at higher frequencies, even if the gated clock doesn’t glitch (which it will without careful design.)

This brings up a common issue: modeling ASIC clock gating on FPGAs. It isn’t really feasible to just define the clock gate in HDL and hope for the best. It needs special handing.

You can model ASIC-like gated-clock behavior in your FPGA using clock-enable flops for your synchronous blocks. This can be dealt with as a synthesis option in your flow, which will identify the gated clock domain and convert its flops to FDCEs. Vivado example: https://support.xilinx.com/s/article/982650?language=en_US

Some FPGAs do support clock gating, using dedicated clock gate resources with predictable timing and glitch-free behavior. More here from Xilinx (look for BUFGCE): https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf ; other FPGAs will be similar.

Note that with BUFGCE, you’re still obliged to meet clock setup/hold from clock enable to clock rising edge. Still, that’s an easier constraint to meet than making an asynchronous clock gate out of fabric logic. If you’re modeling an ASIC you have to account for the difference between BUFGCE and whatever standard cell you’re using in the ASIC.

Finally, you asked how clock gating is actually done. Tl, dr: the enable is latched to prevent disturbing the clock pulse with a glitch. More here: https://anysilicon.com/the-ultimate-guide-to-clock-gating/

Answer 2

It is bad idea to add logic gates in clock signal path.

Do not add logic gates to your signal path. Strategically placed clock-gating and clock-divider are sometimes exceptions, but should be used minimally if ever. The exceptions are more likely to be acceptable for large ASICs where power is a concern. FPGAs and small ASICs generally discourage any logic added to the clock.

How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or disabled?

On ASICs clock gating is achieved with a negedge flip-flop and an AND gate (low when disabled) or posedge flip-flop and an OR gate (high when disabled). Glitches are avoided because the toggle to the enable/disable happens when there is no impact on the output. If you find an FPGA that supports clock gating, then it likely does it the same way.

If you are to use clock gating, it needs to be done to large modules; not individual flip-flops. Adding any logic to a clock creates additional timing offset between gated-clock circuits those using the clock directly. If your synthesis tool does not have great clock gating support, then there is a chance it will mess up your clock tree and will require async FIFOs between modules of different gated-clocks even if the are derived from the same clock.

Answer 3

It is bad idea to add logic gates in clock signal path.

In an FPGA, not only is it a horrible idea, the design software should not let you do it.

how does it prevent glitch in the output signal i.e the gated clock as it is enabled or disabled?

It doesn't. What you do instead of gating the clock is to enable the logic which the clock drives. Don't worry about gating the input logic to a flip-flop, either. Just use a flip-flop with an enable input and drive that.