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I have an engineering background, but close-to-zero practical experience with discrete electronic circuit design.

schematic

simulate this circuit – Schematic created using CircuitLab

Regarding the above schematic, let's say I have a P-MOSFET (type SiA441DJ), a 10 V power dupply, and an STM32 microcontroller with 3.3V logic level.

Very simple, I guess.

If I use a GPIO configured as open drain output, not push-pull, and use a pullup resistor between the gate and source of the P-MOSFET, it shuld be possible to directly drive the P-MOSFET from the microcontroller, without extra driver circuitry. (Except a 100 OHM resistor between the GPIO and the gate for "safety" and a pullup.)

The pullup is to put the gate voltage for the off-state.

It it OK to do so? Am I correct or am I missing something?

Regarding the microcontroller STM32F103, the GPIO output driver circuit looks something like this:

GPIO output driver from STM32 Ref. manual RM0008

(GPIO output driver from STM32 Ref. manual RM0008)

So, what I understand (or misunderstand :-) ):

If I use open drain configuration, the P-MOS of the GPIO driver is not conducting, thus open, thus a not existing. So if the GPIO output level is High, also the N-MOS is open, i.e. "not existing". So what's left is the Protection diode, which ties the pin to 3V3. OK then, I understand this doesn't work. Means, the "open drain" configuration is limited to the GPIO output logic.

So my conclusion: I can't directly drive the P-MOSFET this way because the protection diode of the GPIO prevents the Gate voltage to raise to V-SUP = 10 V. That's why I need an additional N-MOS (or NPN) to get a "true open drain", not limited to GPIO hi-voltage level ... That makes sense to me...

Am I right?

I am asking this because lots of examples I found for doing this looks much more complicated, at least using, for example, an N-MOSFET to drive the gate of the P-MOSFET.

Note: A very similar question is here: Can you drive a MOSFET directly from a microcontroller? but is hasn't been answered. The answers had been altered.

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  • \$\begingroup\$ I can refine my answer why not if you have a specific STM32 microcontroller model number and can define which specific IO pin you are using. Some pins are not 5V tolerant, some are. None of the pins are true open-drain pins anyway. \$\endgroup\$
    – Justme
    Nov 17, 2021 at 13:29
  • \$\begingroup\$ For the special case where VSUP and the micro's VCC are the same ... yes. Otherwise ... not without some kind of level translator. An open-drain or open-collector output like the 7407 (and a pullup) would work for low speed switching. \$\endgroup\$
    – user16324
    Nov 17, 2021 at 13:50
  • \$\begingroup\$ Thank you, I edited my question and added details about the GPIO driver. \$\endgroup\$ Nov 17, 2021 at 14:04
  • \$\begingroup\$ Oliver, If we are done here, please take note of this: What should I do when someone answers my question. If you are still confused about something then leave a comment to request further clarification. \$\endgroup\$
    – Andy aka
    Mar 18 at 10:24

5 Answers 5

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If I use a GPIO configured as open drain output, not push-pull, and use a pullup resistor between the gate and source of the P-MOSFET

and

It this OK to do so ? Am I correct, or am I missing something ?

Theoretically yes but, the devil's in the detail; when the open-drain output from the MCU is not pulled down, it will try to rise to your power voltage level i.e. it will try to rise to 10 volts. This may exceed the absolute maximum voltage level on that MCU IO pin or, there may be a bit more leakage current into that pin that makes the switch less effective. It's all down to the details in the MCU's data-sheet.

I am asking this because lots of examples I found for doing this looks much more complicated, at least using, for example, an N-MOSFET to drive the gate of the P-MOSFET.

This is the normal way because of the reasons mentioned above. See also the notes I added to the new diagram provided by the OP:

enter image description here

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This is a good spot for the oft-neglected common base configuration:

schematic

simulate this circuit – Schematic created using CircuitLab

Assuming 3.3V CMOS GPIO, if the GPIO pin is low, you turn on Q1, pulling M1's gate down to ~3V. If the GPIO pin is high, you turn off Q1, and R2 pulls M1's gate up to V-SUP.

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  • \$\begingroup\$ Why is R1 needed? \$\endgroup\$
    – bigjosh
    Nov 23, 2021 at 19:33
  • \$\begingroup\$ @bigjosh R1 controls the current through Q1. When Q1 is on, its emitter is going to be at ~2.6V, a diode drop below the 3.3V rail. The GPIO pin is going to try to pull this down to zero, so you get uncontrolled, possibly damaging current into the GPIO pin if you don't have some resistance here. \$\endgroup\$
    – John Doty
    Nov 23, 2021 at 20:09
  • \$\begingroup\$ Makes perfect sense. Thanks! \$\endgroup\$
    – bigjosh
    Nov 24, 2021 at 21:07
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No, the FET would always be on, no matter if MCU output 3.3 V or 0 V to gate. The Vgs would be 6.7 V or 10 V.

Also the pull-up to 10 V would always force overvoltage on MCU pin, but would also limit injection current into MCU pin. Some 5 V tolerant MCU pins are not diode protected to digital supply voltage, so it could damage MCU pin.

The MCU does not have true open drain outputs, it will just not drive high if you configure it as open drain.

The MCU IO pins just can't have a pull-up to 10 V.

STM32F103 absolute maximum ratings: VDD + 4.0 V on 5 V tolerant pin. 4.0 V on other IO pin. 5 V tolerant pins have no diode so they don't clamp current to VDD. Other IO has 5 mA clamp limit. These are out of specs ratings already, these must never appear in normal operation.

Nominal operating conditions: Standard IO max VDD + 0.3 V. 5 V tolerant IO max 5.5 V And to go past VDD + 0.3 V on a 5 V tolerant pin, internal pull resistors must be disabled.

So no, not possible to drive a PFET with 10 V on source.

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  • \$\begingroup\$ He did say an open drain GPIO. Then again, as per Andy aka answer, if there are internal protective diodes on the open drain GPIO then you're right. \$\endgroup\$ Nov 17, 2021 at 13:20
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    \$\begingroup\$ @DanielChisholm I know he did. It does not make a difference. The MCU can't have a pull-up to 10V on any pin. Not on 5V tolerant pins, not on 3.3V tolerant pins. \$\endgroup\$
    – Justme
    Nov 17, 2021 at 13:23
  • \$\begingroup\$ "the FET would always be on": Is this because of the Protection diode of the GPIO ? \$\endgroup\$ Nov 17, 2021 at 14:12
  • \$\begingroup\$ @OliverRichter Yes, that applies to a non-5V tolerant pin, the IO protection diode would prevent IO pin voltage from rising above 4.0V, which would result into clamping current which should be avoided. A 5V tolerant pin would not clamp, it would be damaged, so you would not do that either. \$\endgroup\$
    – Justme
    Nov 17, 2021 at 14:26
  • \$\begingroup\$ Even on 5V tolerant pins there will usually be some sort of ESD protection to limit the voltage to some safe value a bit above 5V, maybe a Zener or something FET-based with the same voltage limiting functionality. So it will pull down on the 10V pullup, and if it is asked to conduct too much current it will blow. \$\endgroup\$
    – bobflux
    Nov 17, 2021 at 18:51
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Controlling the Pmos from 3v3 leads to very ugly workaround it can bring many trouble. Much more clear is controlling with additional NPN/Nmos transistor like below.

schematic

simulate this circuit – Schematic created using CircuitLab

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Generally no, if the load voltage is above the controller GPIO logic level, and the GPIO has protection diodes, which is usually the case.

But as an exception, yes if the load Voltage is in the range of the controller GPIO logic level. However, this is only a special case (it is uncommon to drive a strong load with the small voltage of 3.3 V for example).

I also found a good source that shows the difference. It shows using an NPN to drive the MOSFET (see under "P-Channel MOSFET with same load voltage" and "Transistor Driver Examples").

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