Can you drive a P-MOSFET as a high side switch directly from a microcontroller?

Question

I have an engineering background, but close-to-zero practical experience with discrete electronic circuit design.

^{simulate this circuit – Schematic created using CircuitLab}

Regarding the above schematic, let's say I have a P-MOSFET (type SiA441DJ), a 10 V power dupply, and an STM32 microcontroller with 3.3V logic level.

Very simple, I guess.

If I use a GPIO configured as open drain output, not push-pull, and use a pullup resistor between the gate and source of the P-MOSFET, it shuld be possible to directly drive the P-MOSFET from the microcontroller, without extra driver circuitry. (Except a 100 OHM resistor between the GPIO and the gate for "safety" and a pullup.)

The pullup is to put the gate voltage for the off-state.

It it OK to do so? Am I correct or am I missing something?

Regarding the microcontroller STM32F103, the GPIO output driver circuit looks something like this:

(GPIO output driver from STM32 Ref. manual RM0008)

So, what I understand (or misunderstand :-) ):

If I use open drain configuration, the P-MOS of the GPIO driver is not conducting, thus open, thus a not existing. So if the GPIO output level is High, also the N-MOS is open, i.e. "not existing". So what's left is the Protection diode, which ties the pin to 3V3. OK then, I understand this doesn't work. Means, the "open drain" configuration is limited to the GPIO output logic.

So my conclusion: I can't directly drive the P-MOSFET this way because the protection diode of the GPIO prevents the Gate voltage to raise to V-SUP = 10 V. That's why I need an additional N-MOS (or NPN) to get a "true open drain", not limited to GPIO hi-voltage level ... That makes sense to me...

Am I right?

I am asking this because lots of examples I found for doing this looks much more complicated, at least using, for example, an N-MOSFET to drive the gate of the P-MOSFET.

Note: A very similar question is here: Can you drive a MOSFET directly from a microcontroller? but is hasn't been answered. The answers had been altered.

Answer 1

If I use a GPIO configured as open drain output, not push-pull, and use a pullup resistor between the gate and source of the P-MOSFET

and

It this OK to do so ? Am I correct, or am I missing something ?

Theoretically yes but, the devil's in the detail; when the open-drain output from the MCU is not pulled down, it will try to rise to your power voltage level i.e. it will try to rise to 10 volts. This may exceed the absolute maximum voltage level on that MCU IO pin or, there may be a bit more leakage current into that pin that makes the switch less effective. It's all down to the details in the MCU's data-sheet.

I am asking this because lots of examples I found for doing this looks much more complicated, at least using, for example, an N-MOSFET to drive the gate of the P-MOSFET.

This is the normal way because of the reasons mentioned above. See also the notes I added to the new diagram provided by the OP:

Answer 2

This is a good spot for the oft-neglected common base configuration:

^{simulate this circuit – Schematic created using CircuitLab}

Assuming 3.3V CMOS GPIO, if the GPIO pin is low, you turn on Q1, pulling M1's gate down to ~3V. If the GPIO pin is high, you turn off Q1, and R2 pulls M1's gate up to V-SUP.

Answer 3

No, the FET would always be on, no matter if MCU output 3.3 V or 0 V to gate. The Vgs would be 6.7 V or 10 V.

Also the pull-up to 10 V would always force overvoltage on MCU pin, but would also limit injection current into MCU pin. Some 5 V tolerant MCU pins are not diode protected to digital supply voltage, so it could damage MCU pin.

The MCU does not have true open drain outputs, it will just not drive high if you configure it as open drain.

The MCU IO pins just can't have a pull-up to 10 V.

STM32F103 absolute maximum ratings: VDD + 4.0 V on 5 V tolerant pin. 4.0 V on other IO pin. 5 V tolerant pins have no diode so they don't clamp current to VDD. Other IO has 5 mA clamp limit. These are out of specs ratings already, these must never appear in normal operation.

Nominal operating conditions: Standard IO max VDD + 0.3 V. 5 V tolerant IO max 5.5 V And to go past VDD + 0.3 V on a 5 V tolerant pin, internal pull resistors must be disabled.

So no, not possible to drive a PFET with 10 V on source.

Answer 4

Controlling the Pmos from 3v3 leads to very ugly workaround it can bring many trouble. Much more clear is controlling with additional NPN/Nmos transistor like below.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 5

Generally no, if the load voltage is above the controller GPIO logic level, and the GPIO has protection diodes, which is usually the case.

But as an exception, yes if the load Voltage is in the range of the controller GPIO logic level. However, this is only a special case (it is uncommon to drive a strong load with the small voltage of 3.3 V for example).

I also found a good source that shows the difference. It shows using an NPN to drive the MOSFET (see under "P-Channel MOSFET with same load voltage" and "Transistor Driver Examples").