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I need to bring the voltage from 0-5 V to 0-1 V so I'm using an op amp, for linearity, in my design. The inverting op amp has a gain = \$-R_1/R_2\$. My output signal is inverted, but I want a non-inverting output. I can add another inverting op amp with unity gain. Is there another way to do it?

enter image description here

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  • \$\begingroup\$ Manny, you will likely want to cope a little better with bias currents than your schematic illustrates (though perhaps you are only showing a behavioral idea.) You haven't specified your accuracy requirements, if any, or precision needs. Nor what the output much drive. I agree that using resistor dividers may present problems, including initial inaccuracy due to tolerance interactions. \$\endgroup\$
    – jonk
    Commented Nov 18, 2021 at 18:40
  • \$\begingroup\$ Jonk, I agree, I'm feeding this input to a XADC of an FPGA where each bit is = 244 µV. \$\endgroup\$
    – Manny
    Commented Nov 18, 2021 at 19:09

2 Answers 2

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That way.

schematic

simulate this circuit – Schematic created using CircuitLab

If you don't like the divider, then you have to use 2 op amps. But you need also a dual power supply +/-.

schematic

simulate this circuit

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  • \$\begingroup\$ I'm trying avoid a simple voltage divider tekscan.com/blog/flexiforce/…. \$\endgroup\$
    – Manny
    Commented Nov 18, 2021 at 18:11
  • \$\begingroup\$ The op-amp buffer prevents the non-linearity with load discussed on the Tekscan web page. You've given us 2 gain requirements: your diagram shows a gain of -0.5 and the first diagram in the answer shows a gain of +0.5 but your text states a gain requirement of +0.2. For the first circuit you'll need to use a modern op-amp with inputs that go down to the negative supply rail (i.e. not a 741) or provide a bipolar power supply. \$\endgroup\$
    – Graham Nye
    Commented Nov 18, 2021 at 18:18
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    \$\begingroup\$ @Manny - what is being shown here is a buffered divider, not just a simple divider. What does the output go to? \$\endgroup\$ Commented Nov 18, 2021 at 19:07
  • \$\begingroup\$ Kevin, it is going to a XADC of an FPGA but, first it passes through an AAF filter. \$\endgroup\$
    – Manny
    Commented Nov 18, 2021 at 19:10
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A voltage divider followed by a unity-gain buffer would do it. Can increase resistor values if you want less dissipation. If you don't want to load the signal at all, use a unity-gain buffer before the voltage divider as well.

enter image description here

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