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It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that?

Clearly, we can reduce one for the input of the first adder, but we are adding an additional inverter to the input of the second adder.

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  • \$\begingroup\$ If you read Rabaey's book, it says "Inverting all the inputs of a full-adder cell also inverts all the outputs". This property has been exploited on all odd cells in the diagram above. On the previous page of the same book, there are equations for the full-adder cell. Are you having difficulty with Boolean minimization? \$\endgroup\$
    – Syed
    Nov 19 '21 at 10:40
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    \$\begingroup\$ Does the answer below address your question? You have to respond to comments/answers without which all efforts made by the community here go useless. \$\endgroup\$
    – Mitu Raj
    Nov 20 '21 at 19:53
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The boolean equation for \$C_o\$ in Full Adder is: $$C_o = A.B + C_i(A+B)$$ Implementing above expression in CMOS logic will give you its complementary version at the output of Full Adder cell: $$\overline{C_o} = \overline{A.B + C_i(A+B)} \tag{1}$$ So you have to add an inverter at the output stage to get \$C_o\$: $$\overline{C_o} \rightarrow \fbox{INVERTER}\rightarrow C_o \tag {2}$$ The author is saying that if you invert all the inputs to Full Adder cell, you wouldn't need an inverter to obtain \$C_o\$, and that's true because if you invert all inputs in \$ \text{(1)} \$ and compute the expression: $$\overline{A'.B' + C_i'(A'+B')} \rightarrow \text{solves to} \rightarrow A.B + C_i(A+B) = C_o$$

The cell outputs \$C_o\$ in essence, and hence you don't need the inverter at \$\text{(2)} \$ anymore.

If you look closely at the circuit, you need to invert inputs only at alternate Full Adder cells.

For e.g., in the first cell, where inputs are not inverted, take its \$\overline{C_{o,0}}\$ output instead of \$ C_{o,0}\$ and feed it to the second cell along with inverted \$A_1\$ and \$B_1\$. Now that all inputs are inverted at second cell, it will give \$C_{o,1}\$ directly the output. In this way, inverters can be avoided at the output of both cells.

You can extend this thought to the chain of 4 Full Adders.

The advantage is that the critical path in the circuit which ripples through the carries: \$C_{i,0}\$ \$\rightarrow \$ \$C_{o,3}\$ now has four inverters lesser, one at each Full Adder cell output. Hence, lesser propagation delay. And of course, at the cost of couple of extra gates if you look closely again.

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