# MC34063 inductor current peak does not match calculations

I am trying to design a voltage inverter based on old/cheap/jelly bean parts. I wanted to use the MC34063. Mostly for learning purposes, so I don't look for easier parts to use for now.

I run the calculations, and I also derived the formulas on the datasheet to really understand the math behind. Then I went to practice, and it seems to work fine - except for a corner case with lower input voltage. FYI, from the following requirements, I have come to the same values which can be extracted from a website like http://www.nomad.ee/micros/mc34063a/index.shtml.

My requirements:

• Input voltage: 4.5V to 9V
• Output voltage: -25V
• Output current: 10mA (before goind DCM) to 50mA at Vin min
• Inductor current ripple: +/- 30% (not important now)
• Output voltage ripple: +/- 1% (not important at all now)
• Switching frequency: 50 kHz

And I used the inverting configuration: With these parts (relative to above picture):

• R3 = 0.33 Ohm
• C2 = 47μF (electrolytic)
• R2 = 49.5 kOhm
• R1 = 2.49 kOhm
• C3 = 680 pF
• D1 = V4PAN50-M3/I
• L1 = SRN1060-221M
• C1 = 47μF (electrolytic)

Specifically, with these values, I get a peak inductor current of 900mA, for a maximum output of 55mA at the theoretical minimum of 4.5V input, considering a 1.3V of saturation voltage of the switch.

The problem

The calculations are made to be sure that the inductor ramp, with the maximum on-time of the switch, is enough to charge the output capacitor at the given voltage, and sustain the given load.

For example, with a Vf of the diode of 0.5V, Vin min of 4.5V, saturation voltage of 1.3V and output voltage of -25V, from (also provided in the datasheet): Which brings to 18sμ of maximum on-time.

From my tests, at 50kHz and with an input of 4.5V I do have a -25V unloaded, but with a few mA drops immediately to -14V.

I can have a 25mA load at -25V only from 6.5V in input.

To be sure that the problem is the inductor that does not have enough time to load, I tried to lower the frequency to 35kHz. Indeed now there is more time, and I can sustain a 25mA load already at 5.9V.

So the question is, if is a problem of the on-time, why the calculations are not fitting the reality by a lot?

If it helps, here is the acquisition of the scope at pin 1 (in yellow) and 2 (in light blue), during the 25mA load, and also showing how we are having a correct maximum on-time: As a side question on something else that is not clear, the "long negative slope" on pin 1 is the current increasing in the inductor, as I think increases the drop on R3. I am just clueless on the meaning of the yellow during the off-time (when the inductor is pushing the current into the capacitor), as I should not see this shorter slope on pin 1. Is this due to some coupled capacitance of the internal Darlington to the input?

• Here are some observations arising from the comprehensive information that you provided: 1] I put your My Requirements data into the referenced online model and got 68 uH for L1. Your part number SRN1060-221M is 220 uH. 2] Your requirements frequency is 50 kHz. In the TI datasheet, section 7.5, fosc max is 42 kHz (typical 33 kHz). 3] <redacted> Nov 19, 2021 at 13:32
• Thanks! 1. Is not the requirement for the -minimum- inductor? 2. On frequency, if I am out of spec it might explain some things, will have to check that. 3. t-on is always greater than t-off, at maximum duty cycles. Double check the inverting application in the same TI datasheet, and the t-on vs t-off graph. The t-on/t-off is -not- the duty cycle. Nov 19, 2021 at 13:41
• Please delete my observation 3] - brain error, sorry! Nov 19, 2021 at 13:48
• One coffee later, hoping brain is fully in gear... Observation 1] and -minimum- inductance. Just to be sure that we're on the same page I'm looking at TI datasheet p. 11, table 9.2.1.2. I'm puzzled by the naming of the entry L(min). To my way of thinking the name should be L(at Vin(min)), or preferably Lmax. My reasoning is like this: broadly speaking (other things being equal), output power goes down as L goes up. So, the calculation is finding the maximum value of L to deliver a given power at minimum input voltage. Summary: I would use a calculated L, or lower. Nov 19, 2021 at 14:16
• Yes, we are talking about the same architecture. I have to try indeed with a similar inductor. But a higher inductor would just give less spikes, the only thing is slowing the time response, or cost and size issues. There are no real limitation on the higher value. It just take more time to charge as the ramps are smaller, but a higher inductor will generate the same voltage to keep the same current going with smaller slopes (see inductor equation).... Nov 19, 2021 at 15:18

Thanks for clarifications in earlier comments. I will attempt an answer which will be qualitative because of the large number of variables under consideration.

if it is a problem of the on-time

At 50 kHz there is a problem of off-time too. 1/f = 20 uS; ton = 18. toff at 2 uS is not long enough for L1 (220 uH) to discharge into the output capacitor C1. I estimate 7 to 8 uS is required (not including unknown Darlington switching times).

At low input voltage (4.5 V) the Ipeak is high (0.9 A). These simple calculations do not include voltage drops across R3 (current sense) and the 0.46 Ohm of 220 uH L1. These losses become more significant at higher inductor currents.

why the calculations are not fitting the reality by a lot?

In summary, I think that L1 is too high, at 220 uH; frequency at 50 kHz is too high; at low input voltage resistive losses must be included in the equations for component values.

Watchpoint: An external current drive transistor might be needed to meet the power output requirement (-25 V, 50mA) at low input voltage (4.5 V).

Mostly for learning purposes

I think your project has been very good for learning, particularly for showing the selections and compromises needed for low input voltage. Very interesting for me, and I hope I have given you some useful ideas.

• Thanks, I hope this post will also help someone else :) So, I remember why I choose 50kHz: the datasheet says it support up to 100kHz. Therefore calculations should match (slopes, timing etc) - hence the doubts I have: is there something else I am missing? I will try at lower frequency as stated in the table and re-design the circuit and will update. Nov 20, 2021 at 18:53
• On the internal BJTs, it should be ok considering the power: the design process is to ensure we are in the voltage limits, and do not reach the 1.5A. The calculations are showing a current peak of 0.9A at 4.5V, so I also don't think this should be an issue. It could not be the most efficient, but the basic functioning should still happen. Nov 20, 2021 at 18:55
• I -think- the table 7.5 of the TI datasheet, shows the frequency variation you might have with a 1nF capacitor only. In my circuit for example, I see variations of 45 to 55 kHz when I set 50kHz. The limits I used to dimension the on/off timing and the capacitor, were from the formula and verified against the first table of 7.9 in the datasheet. Nov 20, 2021 at 19:15
• I updated the question, as I have partially answered to myself, if you are interested. Nov 22, 2021 at 22:42
• @thexeno Thanks for progress update, very interesting. I will look out for your next question. Nov 23, 2021 at 16:59

I have found the issue. This will translate into another question but I will considered answered this specific one, to not change the entirely the subject and leave it available for who might experiment with the same part in the future.

So, if the frequency choice was not optimal but still in the boundaries of what possible from the chip, I have instead chose an unrealistic on-time/off-time ratio of 7.9, while the IC can do a (max!) of 7.5 and in this case, one should design considering the worse case boundary of 5.2

The reason why I don't reach the right power at the lower input voltage, in fact, is due to the timing circuitry which does not reach more than a measured value of 5.27 ---> To verify this and apply the formula of

$$\ \frac{t_{on}}{t_{off}} = \frac{|{V_o}| + V_{diode}}{V_{in}-V_{sat}} \$$

I measured the diode forward voltage, and seemed to be, at max load and minimum input voltage (where you get more peak current), of around 0.4V. I did this measurement with different acquisitions and comparisons due to dealing with 25V to measure a 0.5V on a difference between two traces which cannot be done just with an AC mode screenshot, but still. Also, the saturation voltage measured during the on time is around 1.6V, measuring the difference between the collector (pin 1) and the emitter, pin 2 ---> Then, I noted the minimum input voltage at which I am able to provide 50mA, and is 6.5V. Putting all these numbers in the formula, I indeed get a on/off ratio of 5.24, which is very close to 5.27, hence I consider the design process correct. There is only open one thing, which is why I see a saturation voltage that high.

I will give an answer in case we find it, or I might ask it in a dedicated question. Thanks who helped in thinking through this.