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I am designing 4 layer PCB which has the following stack up structure:

  • Layer 1 (top layer) signal
  • Layer 2 (inner layer 1) power plane
  • Layer 3 (inner layer 2) ground plane
  • Layer 4 (bottom layer) signal (consists of an RF antenna track)

I have connected all the 5V and 3.8V connections from top/bottom layer to power plane through the through hole vias. As per the layer stack up, power plane and ground plane both are adjacent to each other and dielectric thickness is 1mm.

  1. Will this create capacitance between PWR and GND planes? Will it create any problems?
  2. Should I remove extra copper from the power plane?
  3. As I have used through hole vias instead of blind vias, there are unused vias (via stubs) in PCB. Can these floating vias cause any problems with the PCB?
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    \$\begingroup\$ Only remove copper on the power-plane layers if it's not connected to the power net(s), and only if it's impossible to find a way to connect it to a power net. But if you find this to be the case there's a strong likelihood that you're not using your power-plane properly. \$\endgroup\$
    – brhans
    Nov 19, 2021 at 14:57

1 Answer 1

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  1. Yes, it adds capacitance between power planes. Two conductors separated by an insulator is a capacitor. It will not create any problems, on the contrary, it is a very much desired property to have distributed capacitance between power planes.

  2. Based on 1), definitely not.

  3. It depends what signals will pass through the vias and will the stubs of a via be harmful. For RF and high speed data signals, maybe, for low frequency stuff, unlikely.

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    \$\begingroup\$ And remember to take into consideration voltage/spacing limits. Such as proper clearance between a 680VDC via and all internal planes. \$\endgroup\$
    – rdtsc
    Nov 19, 2021 at 12:53
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    \$\begingroup\$ Another, often forgotten reason for 2) is that the average copper distribution should be symmetrical relative to the middle of the stack, to reduce warping. \$\endgroup\$
    – Maple
    Nov 19, 2021 at 15:01
  • \$\begingroup\$ Thanks for your response. Actually i am new for 4 layer pcb. So, i don't understand that what is right and wrong in my design. Can you please explain me my related to, 1) my 4 layer stack up which i chose 2) If i use power plane as a signal layer and trace the power tracks in pwr layer 3) extra unused vias can cause any problem to RF antenna track and connector 4) you told that the capacitance will create because of pwr plane and gnd plane are adjacent to each other, so this capacitance is normal or i have to make any changes in my design for that? Hope you answer all, it request \$\endgroup\$
    – Devang Parekh
    Nov 21, 2021 at 17:35

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