# SCR latching current and holding current equivalent definition

understanding the definitions of Latching and holding current. suppose a particular value of the gate current I_g is given. Now that we increase the voltage across the SCR from 0V and onwards. Forward leakage current starts conduction. And after a certain point it increases further slightly. As indicated by the curvy lines.(transition state)

if we further increase the voltage, the current suddenly becomes "significant".(I'll call it point "p") Now my question is , is the current at this point is latching current? in other words, is it true that the turn on current and latching current the same? more precisely, is it correct so say, if gate voltage is given then turning on the SCR implies latching the SCR as well.(gate signal independency).

coming to holding current. if gate signal is not present then if we lower the anode current below holding current it will turn off. But how about the case if we don't remove the gate signal? will it be turn off in this case?

• It would be helpful if you provided the source for your document. Hopefully, a source that includes a context. At a guess, those "curvy lines" represent the four different quadrants for the gate. But I'm having trouble making out your questions. While I think I have some details, I'm not sure about the rest. So it's like having half a picture. Are you aware that any externally applied gate current lowers the break-over voltage? The more, the lower it gets?
– jonk
Nov 19, 2021 at 20:50
• @jonk: "Are you aware that any externally applied gate current lowers the break-over voltage? The more, the lower it gets?" No. Break-over voltage is the voltage at which the SCR "turns on" with gate current = 0.
– user80875
Nov 20, 2021 at 2:28
• @CharlesCowie I was able to find something supporting my vague thought. See 3rd paragraph under SCR triggering / firing summary.
– jonk
Nov 20, 2021 at 2:58
• @jonk: Yes, I guess you can say that is what the gate current is doing, but it is not good to just supply enough gate current to have the SCR break over and conduct. The gate pulse needs to be strong enough to quickly lower the effective blocking resistance drastically.
– user80875
Nov 20, 2021 at 4:18
• @CharlesCowie Agreed. The whole thought in my head was not well-stated -- not as well as I should have done, anyway. It just crossed my mind for a moment as "another way to look at things." (I'm always trying to find 50 ways to see anything. It's a life's work, so to speak.) I was fortunate enough to be able to find a web page that was "close enough" to what I was thinking, on short order. Anyway, thanks for taking a moment for me. I appreciate it (and undeservedly honored by it.)
– jonk
Nov 20, 2021 at 4:20