# LM53603 capacitors package size

in my project Im using the LM53603 voltage regulator.

In the datasheet's typical application I see 3 capacitors on both the VIN and VOUT lines, respectively called Cin and Cout.

In the physical layout at p.32, three of those two are a bigger package size despite (allegedly) being the same value. In section 9.2.2.2 it explains that having bigger package size helps avoid a significant drop in capacitance when power is applied, despite not citing any recommended package sizes apart from C3225X7R1C226M250AC (TDK) in the Recommended Output Capacitors table, which is 1210 size.

My question is, what size should I use for the smaller capacitor, if I use the recommended 1210 size for the two bigger ones? Does that matter? I would preferebly use 0603 since thats what Im using for the rest of the board.

Also, in the physical layout the smaller Cin cap seems to overlap one of the IC's pads, is that a mistake or should that cap be on the other side of the board?

Thanks.

• What does your capacitor datasheets or technical information tell you about the capacitance at operating voltage? Nov 20 at 11:48
• Search term for you: high-k dielectric. The ones that allow you to make higher capacitances in smaller areas tend to also have much worse stability with DC bias. Nov 20 at 15:39

The case size as such matters only for ESL and that is of no concern in this application.

The datasheet had to give acceptable recommendations for the entire range of input and output voltages whereas in your application you will have precise specs. Therefore, just make sure that the caps you select have the correct capacitance when biased at the intended operating voltage. Reputable capacitor makers provide $$\C(V_{DC})\$$ curves to judge this. You will find that class 2 (e g. X5R) and class 3 dielectrics lose much of their capacitance at DC bias, and more so if the package is small.

E.g. when working at 5V, a 4.7uF 1210 50V capacitor might indeed have larger capacitance than a 10uF 0603 10V capacitor.

• You will find that class 2 (e g. X5R) and class 3 dielectrics lose much of their capacitance at DC bias, and more so if the package is small. Is this the reason behind having multiple capacitors in parallel on the input/output? Nov 21 at 10:33
• @Steve Well one could have one 1812 or other large package as a single capacitor. but sizes larger than 1210 are rathrr uncommon due to a larger risk or cracking due to stress. Therefore, it is quite common to put many caps in parallel if one needs a largish capacitance. It also allows more flexibility in how to arrange them and use board space efficiently. The latter if done smart, can lead to lower ESL than for one large package. Nov 21 at 12:09