# Turning on SCR without latching it

The picture shows a typical SCR circuit. I have already simulated this circuit in multisim. Since multisim assumes this to be an ideal SCR (zero voltage drop for example,) the characteristics may not be the same in practical situation. I'm asking this question to know the practical situation.

It is given this SCR has a latching current of 10mA. If I trigger the SCR, the multimeter shows a reading of 20mA in the figure, and latches. This is expected. When I change R_1 to 10k and try to trigger it by pressing S_2, initially it shows a reading of 2mA, but doesn't latch. It comes to a few microamperes if I release the switch. That is also expected because it is way lower than the latching current.

In the second case, is it fair to say that "the SCR turned ON" while pressing the switch but it just didn't latch? To be clear, what do we precisely mean by "turning ON"? The book says it is just switching from blocking state (which I can understand as few microampere state) to "significantly" high current conduction mode. What is the value of this "significantly" high current? Is there a minimum "turning ON" current below below which one can say the SCR is off?

• This graph from Wikipedia, SCR explains a lot.
– jay
Nov 20, 2021 at 16:09
• I don't think there is a standardized definition. “When I use a word,” Humpty Dumpty said in rather a scornful tone, “it means just what I choose it to mean—neither more nor less.” The SCR is certainly conducting when the current goes up by an order of magnitude or more from the leakage current, whether it's "on" or not is arguable. Nov 20, 2021 at 18:13
• The "ON state" is a resistance that means conduction vs blocking and that is defined by the log incremental slope of Fig 3 in the spec and is bound by thermal limits and $I_H$, the max holding current at Temp. with no trigger condition. FWIW @SpehroPefhany Nov 20, 2021 at 18:45
• @TonyStewartEE75 The GE SCR manual definition requires the voltage across the SCR to be low, which means if there's a short in the load it's not "on". It's a functional definition based on the intended normal operating mode (latched, with low drop). Also excludes intentional operation of the SCR before regenerative action as a high-voltage transistor or remote-base transistor. Nov 20, 2021 at 19:00
• If the GE manual said there no output voltage drop, then there is no holding current which is an inclusion boundary condition to my definition of ON. I think they would agree. FWIW @SpehroPefhany Nov 20, 2021 at 19:06

Because of the resistance to latching ,

Is there a minimum "turning ON" current below which one can say the SCR is off?

YES but there are two parameters to turn it ON and keep it ON with no input current.

1. minimum trigger current, $$\I_{GT}\$$ required to latch 100 ohms
2. minimum holding current, $$\I_H\$$ = 5 mA (max) in the example below @ 25 °C

## More details

to really understand simplify how transistors work using impedance ratios.

This trigger current also is affected by the load resistance so it will define this load as there is a current gain effect to overcome a load loss to reach a base voltage that accelerated positive feedback to latch. There is also the leakage or "Early effect" in the uA current range with many different variables that affect the switch, R(ON). This Ron value declines as device power rating goes up, approximately by R ~ 1 / Pmax

This could be equated to the threshold of impedance ratios of load to SCR switch and the current gain increases that threshold to the input.

How can SCR junctions be triggered?

1. gate triggering input current, $$\I_{GT}\$$
2. Overvoltage triggering on output, $$\V_{DRM} (+)~ or~ V_{RRM} (-)\$$
3. dV/dt triggering from the load side
4. thermal triggering (NTC effects on PN junction.)
5. Optoelectric gate triggering

How can latches be held after triggering?

By Holding current $$\I_H\$$.

• This stimulates the positive feedback current to keep the driver output biasing the input. An SCR is made from two transistors that share in PNPN arrangement, similar to the substrate of all CMOS chips that need 0.2V diode clamps to prevent this failure mode from signals outside Vdd to Vss. ("shoot-through" or SCR latch effect)

Let's only look at the DC condition for 1. above and look at the cheapest SCR

*from spec Fig 3. (1A * 1.2V ~1watt so I expect Ron ~ 1 ohm with a wide tolerance) However the estimate of Ron is a dynamic function of load current and incremental resistance may range from 3 Ohms at low current to 0.3 ohms at extreme pulse loads.

What is gate input impedance worst case at trigger threshold?

$$\R_{IN}=\dfrac{V_{GT}}{I_{GT}}= \dfrac{0.8~V}{200~uA}=4~k\Omega,~~R_L=100~\Omega\$$ @ 25°C, impedance ratio Rin/out =40 until triggered then input can be 0 uA but there will be an internal feedback voltage if the gate is opened and biased by holding current.

What is the switch Ron resistance?

Using a linear diode resistor model of Vtm=0.7V + I*Rka, we can estimate output ON resistance for Rka

{k from the german spelling of cathode to anode.}

$$\R_{KA}=\dfrac{V_{TM}-0.7V}{I_{TM}}= \dfrac{1.7V-0.7V}{1.0A}=1.0 \Omega \$$ Which agrees with my estimate.

So what is the effective resistance gain of this SCR latch?
Rin/Ron = 4k/1= 4000 from trigger to Ron.

What is the power gain of the switch? Using fig 3 again with the hotter plot.

The incremental slope is the tangent over a small range for a log-lin plot of Ron=ΔVt/ΔIt. This example is from 3 Ohms to near 0.25 Ohm at the top.

$$\\frac{P_D }{ P_{trig}}= \frac{V_T*I_T}{V_{GT}*I_{GT}}= \frac{1.2 ~W}{0.00016~W}=7500\$$

This is the best-case power-gain computed but pulsing higher currents to guarantee faster gate turn-on from input capacitance is where one you expect to derate these ratios. But due to the diode drop, these are not as good a switch as Power Mosfets or even common-emitter Rce, but they are latching and that's the tradeoff.

All the other parameters are given for pulsing, derating, dynamic and thermal effects beyond 1A which raises Ron from secondary junction effects.

But it is useful to understand current triggering and voltage triggering are almost the same thing related by this threshold resistance to make linear out of exponentials.

# Conclusion

What causes this holding current?

If you look back at the Rin/RLout = 40 resistance ratio to trigger the output and apply that to holding current, Ih=5mA, 5mA/40 = 125 uA you get a fraction of the 200 uA input trigger current but due a higher output voltage, this is resistance and current ratio is all that is necessary to keep the input self-biased from positive feedback. After all, transistors are Vbe-controlled current sinks that we can model with current gain and impedance effects.

This internal positive feedback is what makes them work as latches.