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I have an SPI line going at a speed of 12Mbit/s on a 2-layer PCB. This is for a product so it needs to pass EMC tests (as well as just work well).

Questions:

  • Should I use series resistors for all the lines or just the clock? Size of resistors? (how many ohms?)
  • Is it important not to change layers for signal integrity?
  • Is it important to avoid vias?
  • Impedance matching?
  • Via stitching?

If all or some of these are overkill for these speeds (?), at what speeds does one need to start to think about this?

The 1st SPI is going to memory and measuring chip and the 2nd SPI to a display

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    \$\begingroup\$ You list frequency but do not list distance so it sounds like you do not know that frequency relative to distance is what determines when you need to care. With only 2 layers though, your options are limited. Why are you even asking about via stitching when it is impossible on 2 layers? \$\endgroup\$
    – DKNguyen
    Nov 21, 2021 at 21:25
  • \$\begingroup\$ Read this: hottconsultants.com/tips.html You can also just get his book. It's good. Your question about vias, and changing layers fall under "changing reference planes", not that it will help you on a 2 layer board where no reference planes can exist. \$\endgroup\$
    – DKNguyen
    Nov 21, 2021 at 21:30
  • \$\begingroup\$ It depends on your PCB design, parts, and distance of the signal. I would Put series termination at the source, adjust the value empirically. make the signal pair with ground/return, and force the return current to that return path (theoretical, but possible). If you can, twist the pair (stitching and switching layers). For 12Mhz with series resistors, I do not think via does too much harm. You can actively reduce the slop, if necessary, by C with the series resistors. All these are hypothetical. \$\endgroup\$
    – jay
    Nov 21, 2021 at 21:33
  • \$\begingroup\$ Thank you for the feedback. Sorry, I am quite new to this so some question might be a bit stupid.. it is about max 20 mm for all signals. would you put the series resistors on all or just on clock? \$\endgroup\$
    – mannen
    Nov 21, 2021 at 21:44

2 Answers 2

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If you don't know if you need resistors or not, draw them in so you don't need to do another board.

Resistor physical size is up to you, and the resistance value can't be known beforehand. it depends on the wiring length, wiring capacitance, load capacitace, even trace width as it contributes to the trace impedance.

It also depends on what devices you have on the bus, and how strong their output drivers are. It's not the speed of clock that matters, it's the speed of the signal rise and fall time that matters. Some MCUs have programmable output strength. And if there are problems, the other wires can cause problems too, not just the clock.

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  • \$\begingroup\$ OK, in what way is the trace impedance important? should it be keept low? shouls i use impedance matching? what impedans in that case? is length matching of SPI lines a good idea? \$\endgroup\$
    – mannen
    Nov 21, 2021 at 22:00
  • \$\begingroup\$ the trace impedance needs to match the terminating impedance. if it doesn't there will be ringing and emi issues. \$\endgroup\$
    – user16222
    Nov 21, 2021 at 22:30
  • \$\begingroup\$ I don’t think your timing margins are sub nanosecond, so length matching over 20mm won’t gain you anything. Just route the tracks and you should be fine. I’d put in series resistors just in case. If the tracks were running 100’s of mm and/or via cables, then i’d be more cautious. \$\endgroup\$
    – Kartman
    Nov 22, 2021 at 3:48
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A resistor on all SPI lines will make edges less steep and that's good for EMC tests.

Start from 1 kOhm.

Use CAT16 or CAT16 that have 4 independent resistors in a single package.

Slow down SPI clock if you can.


You can change layer because at 12 Mbit/s you don't really have signal integrity issues.


The bottom layer of your PCB should be GND.

The top layer should be used for routing.

Fill all empty PCB areas of your top layer with GND and then use stiching vias to connect these areas to the bottom layer.

I understand that in a 2-layer PCB you will have to use vias. Minimize the number of vias and the length of the traces on the bottom layer.


Power integrity is very important as well.

Add capacitors close to the integrated circuits or modules that switch faster: SPI modules for example.

Put a100 nF ceramic capacitor in parallel to 10 to 470 uF capacitor on the VDD of those chips/modules


Keep fast signal's PCB traces short.


Design your product as small as possible.

Small products have spurious emissions in the GHz range and that will raise up the chances to pass EMC tests.

Smaller = Cheaper = Better = Boss happy = EMC compliant product.

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    \$\begingroup\$ Series resistors are definitely the simplest way to go here. 1kOhm series resistance is a bit high for 12 MHz or ~40ns time per level on CLK line. I would consider it the absolute max series resistance. Something like 220R would also damp enough. \$\endgroup\$
    – tobalt
    Nov 22, 2021 at 7:05

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