I know that current mode buck regulators are generally stable as long as they're actually operating in current mode (i.e. the inductor ramp current is large enough to prevent slope compensation from dominating the switching behavior). The LTspice help file explains this in the section about using Middlebrook's method of injecting a test voltage source to find the loop gain:
This means that the loop is stable and it isn't possible to synthesize component values since the loop is stable for all component values. This argument is basically pointing out that as soon as it is possible to describe the SMPS in the frequency domain, there are no stability problems, i.e., that the frequency domain is not an effect way to analysis a SMPS.
But I wouldn't say it's completely ineffective—I'd like to know how much phase margin I have since the output capacitors in this design will be low-ESR, and what value, if any, I should use for the feedback divider bypass capacitor.
So, assuming that my buck converter is operating in current mode, I modeled it like this, with the control-to-output transconductance \$G_{mod}\$.
From this I would expect to get this loop gain, neglecting the negligible load of the feedback divider:
$$ G_{loop} = \frac{G_{err}R_{comp}\left(s+\frac{1}{R_{comp}C_{comp}}\right)G_{mod}\left(s+\frac{1}{R_{div1}C_{comp2}}\right)}{s C_{out}\left(s+\frac{1}{R_{load}C_{out}}\right)\left(s+\frac{1}{R_{div1}C_{comp2}}+\frac{1}{R_{div2}C_{comp2}}\right)} $$
And actually, it might be simplified even more because the MAX16956 (the internally-compensated regulator I'm designing around) specifies that the error signal is integrated, which might mean \$R_{comp}=0\$ so that the error amplifier is truly just an integrator.
So after working through this I went to the SIMPLIS schematic provided by Maxim Integrated, followed the instructions for ac analysis, and adjusted it for my requirements:
I quickly became very confused by the results, which look like this:
The document that comes with this SIMPLIS schematic when I downloaded it from Maxim shows a similar Bode plot. However, shouldn't there be 90° of phase shift and a -20 dB/decade slope from dc due to the pole at the origin?
I'm imagining how the circuit would behave if VAC1 were dc. The regulator would try to bring the feedback input back down its reference voltage by lowering \$V_{OUT}\$ to \$V_{OUTnominal}-V_{AC1}\$. This would bring the positive terminal of VAC1 down to \$V_{OUTnominal}\$. Using Middlebrook's method to find the loop gain, we would use the “ac” values of the two nodes:
$$ G_{loop} = \frac{V_{OUT}-V_{OUTnominal}}{V_{OUT}-V_{OUTnominal}+V_{AC1}} = \frac{V_{AC1}}{V_{AC1}-V_{AC1}} = \frac{V_{AC1}}{0} = \infty $$
Which is what we'd expect, since there's a pole at dc. I am new to SIMPLIS but I believe the ac response is generated from repeated transient simulations, similar to how it's done in LTspice. In the Bode plot I'm getting, I only see the pole due to the output capacitor and load resistor, and the pole from bypass capacitor C3. Perhaps I'm misunderstanding something, or the simulation is incorrect? Unfortunately the regulator model is encrypted so I can't see what's going on inside it.
EDIT: I'm expecting a Bode plot like the one in Figure 2-3 of TI application report SLVAE09B.
EDIT: Well, the variant of MAX16956 I wanted went out of stock in the meantime, and I switched to ST's A6985F, which is not internally compensated, so there is a lot more information available. In the datasheet, I saw this diagram of the transconductance error amplifier:
There is a resistor in parallel with the current source, which means the pole is not located at the origin anymore. Might this explain it?
