I'm trying to understand the effect of a capacitive load at the output of an inverter.
And how does it affect the output signal when this capacitive load is high and when it is low?
Could anybody explain that to me?
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\$\begingroup\$ Inverter you mean like power inverter or digital inverter (i.e. not gate)? In the latter case, any digital electronics books is gonna cover this. \$\endgroup\$– edmzCommented Nov 22, 2021 at 17:53
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\$\begingroup\$ I mean in the CMOS Inverter with NMOS and PMOS transistors \$\endgroup\$– Mohammed AmanCommented Nov 22, 2021 at 18:36
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\$\begingroup\$ Well then you need to go through CMOS theory. It's derived how long it takes for the inverter to compute the NOT operation depending on load capacitance (i.e. fan out essentially). Since it goes like 0.6*Req*C, the higher the load, the longer it takes of coursee. \$\endgroup\$– edmzCommented Nov 22, 2021 at 18:50
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