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Folks, I am planning to design 4-layer PCB.

I came across the following website which has excellent pointers:

http://www.hottconsultants.com/techtips/pcb-stack-up-2.html

Here is an excerpt:

A fourth possibility, not commonly used, but one that can be made to perform very well, is shown in Fig. 4. This is similar to Fig 2, but with the power plane replaced with a ground plane, and power routed as a trace on the signal layers.

Figure 4 from web site

This stack-up overcomes the rework problem mentioned before, and still provides for the low ground impedance as a result of two ground planes. The planes however do not provide any shielding. This configuration satisfies objectives (1), (2), and (5) but not objectives (3) or (4).

So, as you can see there are more options available, than you might have originally thought, for four layer board stack-up. It is possible to satisfy four of our five objectives with a four layer PCB. The configurations of Figures 2, 3b, and 4 all can be made to perform well from an EMC point of view.

My question is why the SIG/GND/PWR/GND variation of Figure 4 in the website is not discussed? Is something fundamentally wrong with the above stack-up?

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    \$\begingroup\$ it's all about reference planes... your high speed signals only care about the nearest plane is how i think of it \$\endgroup\$
    – vicatcu
    Nov 22, 2021 at 22:49
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    \$\begingroup\$ Nothing really wrong with it (Figure 4). But having 2 gnd planes right next to each other really doesn't help things at all. From a power distribution network (PDN) viewpoint, you're better off with a GND/PWR plane configuration, on layers 2 & 3. \$\endgroup\$
    – SteveSh
    Nov 22, 2021 at 22:50
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    \$\begingroup\$ And for high speed signals, a power plane is as good as a GND plane for SI purposes. They both serve to provide the return path for the high frequency components of signals - minimizing loop area => minimizing path inductance. \$\endgroup\$
    – SteveSh
    Nov 22, 2021 at 22:52
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    \$\begingroup\$ Please just post your links as links. It makes it much easier to find out what you are talking about. \$\endgroup\$
    – The Photon
    Nov 22, 2021 at 23:00
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    \$\begingroup\$ Isn't SIG/GND/PWR/GND, Figure 1 and 2? Which are discussed. \$\endgroup\$ Nov 23, 2021 at 0:09

1 Answer 1

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I have heard some issues with sig/gnd/pwr/sig. You have to remember that a signal on layer 4's path to ground is thru the nearest bypass cap. With sig/gnd/gnd/sig-pwr you can shorten the return path by just putting a ground via from layer 2 to 3 right next to your signal via going from 1 to 4.

I guess you have to figure out if your signals are fast enough to really worry about it though. There are millions of 2 layer micocontroller boards out there and the world hasn't ended yet.

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