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I'm rather new to electronics and I don't understand how the output is formed in this question:

question figure

I'm providing an input (Vin) of 5V peak-to-peak sine wave with a 1kHz frequency.

I simulated this in LTspice but I did not expect the output to be anything like that (picture of waveform below.)

The thought process I used was: The diode will be forward biased whenever Vin is 0.6V with respect to ground and the output voltage will be 0.6V. When the input is below 0.6V and in its negative half cycle, the diode will be reverse biased and the current flows through the resistor and Vout is the same as Vin. However, once Vin reaches it's maximum negative value of -2.5V, the capacitor starts discharging and Vout becomes exponential in nature and this continues for each cycle.

The output I got was completely different:

Output waveform (green) imposed over Vin (blue)

Output waveform (green) imposed over Vin (blue)

Can someone please explain where I went wrong?

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  • \$\begingroup\$ For a good understanding, did you consider the behavior at the start of your simulation ? What happens if the generator starts at its maximum value? \$\endgroup\$
    – Antonio51
    Nov 23, 2021 at 9:09
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    \$\begingroup\$ You might find it interesting to view this circuit in Falstad's circuit simulator. I notice that the capacitor's voltage remains nearly constant, and that it charges (through the diode) much more abruptly than it discharges (through the resistor). \$\endgroup\$ Nov 23, 2021 at 15:47
  • \$\begingroup\$ Any current flow through the capacitor causes it to charge or discharge. It doesn't matter whether it is through the resistor or through the diode. \$\endgroup\$ Nov 23, 2021 at 17:09

4 Answers 4

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It's true that the output can never exceed 0.6V, but you have neglected the action of the capacitor with that constraint.

Ignoring the resistor for now, whenever \$V_{IN}\$ rises above 0.6V, to its peak value of \$V_{IN(MAX)}\$, the capacitor will charge up very quickly to \$V_C = V_{IN(MAX)} - 0.6V\$.

That's a DC charge that remains there even when \$V_{IN}\$ drops back below its peak value.

Consequently, as \$V_{IN}\$ falls again, so that \$V_{IN} < V_{IN(MAX)}\$, the output potential \$V_{OUT}\$ is now lower than \$V_{IN}\$ by an amount equal to whatever voltage \$V_C\$ the capacitor initially charged to.

Also, when \$V_{IN} < V_{IN(MAX)}\$, the diode never again becomes strongly forward biased, and no longer plays a role.

Following that first excursion of \$V_{IN}\$ to its maximum \$V_{IN(MAX)}\$, which caused the capacitor to charge to \$V_C\$, the diode is mostly reverse biased, and the relationship between \$V_{IN}\$ and \$V_{OUT}\$ becomes:

$$ \begin{aligned} V_{OUT} &= V_{IN} - V_C \\ \\ &= V_{IN} - (V_{IN(MAX)} - 0.6) \end{aligned} $$

If you examine that expression carefully, you'll see that this means the input signal is shifted down in potential exactly enough for its peaks to just touch +0.6V.

While that may not be what you intended, it is interesting to note that by flipping the diode polarity, you can shift an output to sit on top of -0.6V:

schematic

simulate this circuit – Schematic created using CircuitLab

This works because the capacitor is charged with the opposite polarity, when the input goes to its most negative potential. Now the capacitor becomes a permanent positive DC offset to the input.

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Since you have it in simulation, you can play with the values and see what happens. Here are plots of 1/100, 1/10, 1, 10, 100 times the RC product in your example:

enter image description here

This is just to add some visualization to @Lorenzo's answer and reference, which provides all the background and a reference, so select that one as correct in preference to this one.

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This is a circuit that is commonly introduced in the 2nd year of community college classes in the US and 1st yr EE courses at 4 yr US universities. At the community college level, at least in some states if not all, the teachers aren't even competent to teach this particular circuit. That last part (teachers that were not competent to handle such a circuit) really shocked me, last year, when I observed 2nd yr students in an actual real-world teaching virtual classroom situation here in Oregon. (I am allowed to take these courses at no cost, now that I'm old enough that no one cares.)

The circuit my own teacher was completely unable to understand and completely wasted an entire class on, was this:

schematic

simulate this circuit – Schematic created using CircuitLab

It breaks down into these parts (where you will see your system):

schematic

simulate this circuit

In your case, it's just the first and last sections:

schematic

simulate this circuit

Note the conceptual transformation above. I've moved the two series components around (the AC source and the capacitor) and I've re-assigned the ground assignment. That ground re-assignment may help in understanding the circuit better.

The capacitor develops a DC bias voltage across it from the half-wave rectification due to \$D_1\$. During one half of the AC cycle, the AC power source charges \$C_1\$ to its peak voltage, less approximately one diode drop (because the charging process has to go through that diode to charge the capacitor.) During the remaining half of the AC cycle, the diode soon becomes reverse-biased (so you can temporarily remove it from your mind) and then what you see is a DC voltage source (which the capacitor holds now) added to an AC source. That sum of DC and AC is then applied across the resistor. So you should expect to see a DC-shifted version of the AC across the resistor load.

However, this only works well if the load is "light" enough. If the resistor load is "heavy" enough, then the capacitor will not be able to keep a fixed DC voltage (charged up from the prior half-cycle) and the load will draw down from the capacitor, causing the capacitor's voltage to reduce gradually during this second half-cycle period. In this case, the capacitor will still get charged up to about the same, as before, but that only happens at the peak of the first half-cycle and immediately starts to decline as soon as the last half of the first half-cycle happens and will continue to decline still more once the diode is reverse-biased. The shape of the capacitor voltage curve becomes odd, too, as it charges up with the first half of the first half-cycle following it towards its peak, then it will follow it away from the peak and, once the diode is reverse-biased will show an RC decay towards the very end of second half-cycle before the next charging portion of the AC cycle kicks back in. So ... hard to describe (as you can see.)

In short, "It gets complicated."

So, as you increase the load (reduce the resistance or otherwise increase the current), then the DC BIAS value will cease being DC and will begin to show a complex AC-seeming component to some DC average. (The load is able to significantly deplete the stored charge on the capacitor between cycles.)

It's far more difficult to compute values for the DC node in the "complex" cases.

When the resistor values are large enough (the load is light enough) then the DC bias node is relatively stable (near DC.) In this case, the DC bias magnitude caused by \$C_1\$ will be about one diode drop less than the peak AC voltage. In your case, this means about \$700\:\text{mV}\$ below the positive end of \$2.5\:\text{V}\$ swing, or about \$+1.8\:\text{V}\$.

So. During the charging (first, positive-going) half-cycle, \$C_1\$ gets charged through \$D_1\$ to about \$+1.8\:\text{V}\$ relative to the ground reference I've placed. And then during the non-charging (second, negative-going) half-cycle, \$C_1\$'s charged voltage is subtracted from the negative peak, so \$-2.5\:\text{V}-1.8\:\text{V}=-4.3\:\text{V}\$ will be the peak voltage across the load resistor. And again, this assumes that the load is light. In your case, this means say about \$100\:\text{k}\Omega\$ or higher.

Let's see a run:

enter image description here

The lower chart shows you the DC bias node. There, you can see that for your two higher resistor values, the DC bias is relatively stable and sits very close to about \$+1.8\:\text{V}\$, as predicted.

(I'll let you think about the cases for the complicated stuff that occurs for your higher-load resistor values. If you set \$C_1\ge 470\:\mu\text{F}\$ you will find that all of your resistor loads will far more be predictable. Give it a try!)

I've +1 your question because it's actually a good question to ask in this context!

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Your circuit is the dual of an envelope follower, i.e. a diode clamp. It has significant uses but as you noticed is not exactly intuitive (as 99% of things containing reactive elements).

First of all the diode will limit the voltage to Vf (0.6-0.7 typical for silicon) so you don't get zero output. That makes the output sine ugly, by the way.

The other thing you are missing is that there is a capacitor in the circuit. Assuming a following high impedance stage (i.e. not a significant load) during the negative semiperiod the capacitor remains partially charged and that will alter significantly the output.

Of course this holds only for certain frequencies (the RC constant of the circuit determine that).

Article explain the working in more details

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  • \$\begingroup\$ oh yes that was a mistake it should have been 0.6V not 0V. Yes, the capacitor should alter the output but is it? How is the output waveform still so sinusoidal in nature? Also, thanks for the article, I will read it! \$\endgroup\$ Nov 23, 2021 at 10:11
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    \$\begingroup\$ why is still sinusoidal: excluding the diode an RC network can only do an amplitude and phase variation, the whole small signal analysis theory rely on this. The diode non-linearity gives the peculiar distortion in the half wave \$\endgroup\$ Nov 23, 2021 at 10:35

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