I am simulating 74HC logic family on LTSpice.

The output of inverters and D-Flip-Flop are normal, but the output of NAND and AND are noisy . How can I compensate or filter that noise?

What kind of problem results in that noise?

Frequency: 1 MHz


Output Voltages of NAND and AND

Inputs of NAND and AND

Edit: If it does matter, you can also see how does v_z oscillate.

enter image description here

  • 4
    \$\begingroup\$ What is the purpose of such a bizarre circuit anyway? If you are trying to create a pair of non-overlapping clocks for some old MOS IC, there are much better ways to go about it. \$\endgroup\$
    – Dave Tweed
    Nov 24, 2021 at 11:58
  • 3
    \$\begingroup\$ Why do you use 2 cascaded inverters as input for 74hc00 and 74hc08 ? Such use introduce a real problem (wanted ?) for the gates after ... Ouputs waveforms at bbm1 and bbm2 are very logical. \$\endgroup\$
    – Antonio51
    Nov 24, 2021 at 13:49
  • \$\begingroup\$ @Antonio51 just typed what I am thinking. There is absolutely no purpose for U9-13 + U16 and Neil_UK explains is the source of what you believe is noise. You are creating a race condition for some unknown purpose. \$\endgroup\$ Nov 24, 2021 at 13:53
  • \$\begingroup\$ I tested with my simulator spectrum-soft.com/download/download.shtm which does not show any ringing ? Just some delays ... I tested at 10 MHz ... \$\endgroup\$
    – Antonio51
    Nov 24, 2021 at 15:07
  • 1
    \$\begingroup\$ @DaveTweed Actually, that’s what I was thinking. How can I create such a circuit? Can you give me some example. \$\endgroup\$
    – elektronik
    Nov 25, 2021 at 12:32

4 Answers 4


If you're trying to create non-overlapping clocks for circuits that need them (e.g., older MOS ICs), the standard way to do that is to use cross-coupled gates to create an R-S flip-flop. NAND gates create non-overlapping active-low clock pulses, and NOR gates create non-overlapping active-high pulses. You can add extra delay in the feedback paths to create extra time in the gap between pulses.


simulate this circuit – Schematic created using CircuitLab

The output of the NAND circuit looks like this:

___      ______      ____
   \____/      \____/
   ______      ______
__/      \____/      \___

The output of the NOR circuit looks like this:

    ____        ____
___/    \______/    \____
__        ____        ___
  \______/    \______/

They are not noisy. They are responding to the signals you have delayed through U9 to U12.

Combinatorial logic responds after a short delay to any change on its input. If closely spaced changes occur, then there won't be time for the output to respond fully, and it can generate outputs without a full logic swing as you are seeing.

It's good that you came across this behaviour now in simulation, and not after your first logic design went onto a board and you found it the hard way.

The lessons of this are several

  • The output of combinatorial logic should be regarded as undefined from the time of the first input to change to a propagation period after the last input to change
  • Don't use such outputs directly, it's best to use them as data inputs to a latch, which is clocked after the propagation delay has expired. If using them for analogue output, say filtered PWM, you may get away with lowpass filtering.
  • Don't ever use such outputs as a clock input to a latch, because the spikes you observe may or may not clock them
  • If you must use combinatorial outputs directly, you can often get away with it by aligning their inputs by producing them all from the outputs of the same latch. However this doesn't work if you're driving something like a 138 3-8 line decoder, which has different propagation delays from different inputs.
  • \$\begingroup\$ If I want to limit latch clocking using e.g. an AND gate, how to avoid spikes on these clock wires? \$\endgroup\$
    – Netch
    Nov 26, 2021 at 12:50
  • \$\begingroup\$ @Netch This is exactly the sort of thing you can get very wrong. You must ensure that any clock enable signal to the gate is latched using the clock signal it is gating to ensure that no runt pulses are generated. Design the timing so that the enable cannot transition when the clock is in the 'wrong' polarity. \$\endgroup\$
    – Neil_UK
    Nov 26, 2021 at 13:07

Note that it's possible to design combinatorial circuits which don't feature such glitches. This is done by including additional terms in your functions's DNF in a way that there's no adjacent non-overlapping regions in the Karnaugh map. Such maps are called "hazard-free" and produce no glitches when any single input changes its state.

here's an example explaining the technique in more details. In your case, the glitches are introduced on purpose (by adding U9-U12), and simply excluding those invertors will produce a functionally-equivalent circuit which will be glitch-free.


Something is very wrong with your simulator. You should be seeing bbm outputs with about 30 nsec pulses.

I suspect that the models in LTSpice are somehow built so that they expect the V- pins on each gate to be at ground, not at -2.5. As a result, the circuits are seeing transitions which just barely under the nominal 2.5 (relative to V-) levels which the IC responds to.

Try redoing your circuit using GND and +5V as your logic supply levels. You'll also have to adjust the DC level on Vx.

Also, just for future reference, when showing traces taken at different points, make the starting point for each trace at the same time. This allow us (and you) to see how different parts of the circuit are behaving at any particular time just by shifting vertically and not having to check the time base.

  • \$\begingroup\$ thanks for the advice. \$\endgroup\$
    – elektronik
    Nov 26, 2021 at 16:12
  • \$\begingroup\$ due to application a -2.5 to +2.5 swing needed. \$\endgroup\$
    – elektronik
    Nov 26, 2021 at 16:15
  • \$\begingroup\$ @elektronik - OK, but you don't need to simulate it that way. Just offset the input by 2.5 volts. \$\endgroup\$ Nov 26, 2021 at 23:45

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