How often does one have to design low level adders or multipliers in digital hardware?

There are a few different techniques to implement adders like ripple adder, carry look ahead adder etc. Similarly there are different techniques to implement multipliers as well which include Booth multiplier etc. I am sure the same applies to other functions like divider and square root etc. There are certainly implementations for these functions that are at transistor level rather than at RTL level.

Digital hardware design is usually done via RTL coding nowadays. In RTL we would just write + or * for sum or product and leave the rest to the synthesis tool. Alternatively, we might instantiate vendor provided IP cores that implement such features so we can have finer control over the resulting design. However, such IP will be limited to features that are implemented by the vendor.

Now my question is, how often do we have to bother about low level details of adder, multiplier, divider etc? If I need finer control I will just use the IP provided by Intel or Microsemi.

Also, I find it strange that these things get asked in interviews when they rarely have real-world applications now.

• They get asked in interviews to see how well you can think on your feet and, to some extent, see how you would approach a problem. I remember when I was asked about writing some pseudo-code to generate a Fibinacci sequence. Nov 24 '21 at 22:56

How often does one have to design low level adders or multipliers in digital hardware?

Rare; but happens. All HDLs I'm aware of will have primitives for addition, and even if they didn't, you'd just specify the math and let your synthesizer find an adequate implementation for your technology (i.e. the specific set of standard cells/logic cells in your ASIC, FPGA or whathaveyou).

Alternatively, we might instantiate vendor provided IP cores that implement such features so we can have finer control over the resulting design. However, such IP will be limited to features that are implemented by the vendor.

Well, if you want anything other than "standard" addition as defined by the language you're using, it's more likely some IP might have the special mode of operation you want...

But honestly, you implement the logic as HDL/RTL, and then come up with an optimized approach for the problem you're actually solving. If it's special, you probably need something special, and that's where you need to start thinking about clocking/space tradeoffs etc.

Now my question is, how often do we have to bother about low level details of adder, multiplier, divider e.t.c?

Define "we"! If you're doing something that demands specific non-standard additions all over the place, then often, else less often. Engineering is specifically not the discipline of solving the same problem that has been solved before with exactly the same tools over and over again, thus, such generalizations never work out.

The generalization that I'll allow myself is that understanding design choices and working principles in adders is certainly a positive indicator for skills in terms of thinking in digital logic. Rippling, clocking, pipelining, technology mapping are all principles that you need a problem of some complexity to understand, but you wouldn't start with something completely out of the world (say, a divider). You'd start looking at ways to implement a 4 bit adder.

If I need finer control I will just use the IP provided by Intel or Microsemi.

Sorry, I don't see how someone else's IP solves your "I need a special non-standard adder" problem.

Also: Having a vague idea of the price of specialized IP cores if not "all inclusive" with your platform, you almost certainly would design that yourself, unless you've got more pots of gold at ends of rainbows than you have HDL engineers.

By the way, the "low level details" of a divider are... involved. Comparing that to implementing a single-clock adder is like comparing building an inkjet printer compared to knowing how to sharpen a quill for writing in ink. There's way more design options you have there. Very few dividers are implemented in a non-clocked single-stage manner. Most dividers are heavily pipelined beasts of complexity! But what you get when you write assign c = a + b; is a simplistic purely combinatorial adder. A single-cycle divider is a dangerous to clock high, space-hungry abomination, even if your operands are only 8 bit!

(PS: Never heard of either companies selling IP / standard cell libraries for that purpose, got a source?)

Good quality engineering design comes from thorough understanding of all aspects of the subject, like most things. You need to know how things work at a low level to know if it's the right choice to employ in a design: whether it will perform well, if there's a much better way.

At the other end of the scale is 'wish list' design, where you type whatever you want in an HDL then can't make it work or meet timing. And the latter is often discovered later in the day, not right at the start when it's being architected. Just putting one's feet up and not even understanding the internals leads to poor quality design.

• I did get asked about them in interview and thought like, I have not had to bother with half and full adders since I left university. What do you think is the best resource for interview related questions. Nov 26 '21 at 9:56
• @quantum231, we're going well off topic here, so this is better suited to a chat. But: good engineering interviews aren't about learning the hot topics, 'revising' the right questions. That'd be to trick them to thinking you're better than you are. Be absolutely genuine, show what you can do. But questions for you: are you driven to want to be a really good engineer? do you want your work to be the best designs/testing/production/etc that there is? If you do, that leads everything. It sounds like 'no', though...the 'bother with' sounds like you see such understanding as beneath you, I'm afraid Nov 26 '21 at 14:32

Since you’re asking this question in the context of a FPGA design, it’s very unlikely that you would get involved in the details of ALU or multiplier design. The FPGA synthesis flow would see the HDL arithmetic statement and figure it out using the most appropriate resource, be it a hard IP or as LUT logic, or both.

On the other hand if you were designing a custom ASIC, you would care not only about how these units are designed, but also how to emulate them in an FPGA using its hard macros (like DSP48 for example.) You would validate both your FPGA and ASIC implementations against a behavioral model, to ensure no subtle differences crept in.

If you're working for Intel, Xilinx or Microsemi, more often than otherwise. (ASIC flows MAY be different, but I think it'll still be rare there)

I have hand-rolled a multiplier - but that was nearly a quarter century ago, when synthesis tools were a lot more rough edged than they are now.