How often does one have to design low level adders or multipliers in digital hardware?
Rare; but happens. All HDLs I'm aware of will have primitives for addition, and even if they didn't, you'd just specify the math and let your synthesizer find an adequate implementation for your technology (i.e. the specific set of standard cells/logic cells in your ASIC, FPGA or whathaveyou).
Alternatively, we might instantiate vendor provided IP cores that implement such features so we can have finer control over the resulting design. However, such IP will be limited to features that are implemented by the vendor.
Well, if you want anything other than "standard" addition as defined by the language you're using, it's more likely some IP might have the special mode of operation you want...
But honestly, you implement the logic as HDL/RTL, and then come up with an optimized approach for the problem you're actually solving. If it's special, you probably need something special, and that's where you need to start thinking about clocking/space tradeoffs etc.
Now my question is, how often do we have to bother about low level details of adder, multiplier, divider e.t.c?
Define "we"! If you're doing something that demands specific non-standard additions all over the place, then often, else less often. Engineering is specifically not the discipline of solving the same problem that has been solved before with exactly the same tools over and over again, thus, such generalizations never work out.
The generalization that I'll allow myself is that understanding design choices and working principles in adders is certainly a positive indicator for skills in terms of thinking in digital logic. Rippling, clocking, pipelining, technology mapping are all principles that you need a problem of some complexity to understand, but you wouldn't start with something completely out of the world (say, a divider). You'd start looking at ways to implement a 4 bit adder.
If I need finer control I will just use the IP provided by Intel or Microsemi.
Sorry, I don't see how someone else's IP solves your "I need a special non-standard adder" problem.
Having a vague idea of the price of specialized IP cores if not "all inclusive" with your platform, you almost certainly would design that yourself, unless you've got more pots of gold at ends of rainbows than you have HDL engineers.
By the way, the "low level details" of a divider are... involved. Comparing that to implementing a single-clock adder is like comparing building an inkjet printer compared to knowing how to sharpen a quill for writing in ink. There's way more design options you have there. Very few dividers are implemented in a non-clocked single-stage manner. Most dividers are heavily pipelined beasts of complexity! But what you get when you write
assign c = a + b; is a simplistic purely combinatorial adder. A single-cycle divider is a dangerous to clock high, space-hungry abomination, even if your operands are only 8 bit!
Never heard of either companies selling IP / standard cell libraries for that purpose, got a source?)