Which of these two SMD decoupling capacitor layouts would have lower ESL?

Question

Usually it is said that small SMD capacitors (e.g. 0603) have lower ESL than larger ones (e.g. 1206). This older question addresses the same problem and the answers confirm what I was thinking, namely that the ESL is determined by the current loop through the capacitor for simple MLCCs.

Now consider the following case of decoupling caps that connect to a power/ground plane pair:

Which capacitor would have lower ESL and why?

Wouldn't the 1206 have lower ESL precisely due to its smaller current loop? Isn't the "capacitor ESL" actually a misnomer because the ESL of the decoupling network is critically caused by its connection to the power rails, i.e. by the number, placement and spacing of the vias rather than the dimension of the capacitor?

The following graphic also seems to suggest that the current loop can be greatly shrunk by placing the vias in tight proximity, because the majority of the current loop is between the vias:

While those packages all have roughly the same size, inductance differs by more than an order of magnitude. It suggest that the current loop area is the only (or by far dominant) contribution to the package inductance. Of course, reducing the package dimensions facilitates achieving smaller total loop areas. However, if this is all there is to it, why do all those guides on decoupling talk about capacitor size so prominently, when it is only a small piece of the whole picture, namely the effort to minimize current loop area? What is the physical reason for MLCC ESL? Is it indeed only the current loop inductance or is there more to it, e.g. some permeability of the capacitor material which of course matters less, the fewer capacitor material there is.

Answer 1

The current loop area is indeed the main contributor to the overall inductance. The dielectric materials of ceramic capacitors like barium titanate (X5R/X7R) or calcium zirconate (C0G) have basically no impact on inductance.

When you go to a MLCC manufacturers website and estimate the ESL of the actual capacitor e.g. by the self-resonance frequency shown in the impedance plot, you need to consider how the impedance measurement was done. An impedance analyzer with a specific test fixture is used. Compensation and calibration is done using open circuit, short circuit and some specific load. In the process, the inherent inductance of the path length of the cap is compensated out of the system. Take a look at Parasitic Inductance of Multilayer Ceramic Capacitors for more details.

With this information we can take a look at an example of inductances resulting from impedance measurements for different package size 100nF caps: _{Source: Kemet KSIM}

So the actual capacitor inductances are in the order of hundreds of picohenry.

What really matters is the total inductance of the current loop which might be in the order of some nanohenry. Now the question is also about pad layout. Lets take a look at a paper from 1999 which shows how the power-plane via placement of an 0805 cap impacts inductance:

You can see that layout is very relevant for the overall inductance. Have a look at the paper ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications for more details.

In essence, the layout is far more relevant for the overall inductance than the actual capacitor. A smaller package of course facilitates a layout with smaller current loops.

Answer 2

It’s hard to precisely say here. The thickness of the board relative to the distance between vias can have a meaningful impact on the effective inductance of the double 1206 vias. The construction of the caps might play a small role.

If one made me guess, I’d say the 1206 would be better but if 5 of us who do high frequency layout were at a lunch table, I’d expect a lot of debate and no clear consensus.

Answer 3

I would vote for 0603 because you can squeeze in two of them in about the same footprint as the 1206, with 4 vias in a criss cross pattern like a poor man's IDC capacitor. This is just handwaving, but it would be interesting to measure it.

Answer 4

Usually it is said that small SMD capacitors (e.g. 0603) have lower ESL than larger ones (e.g. 1206).

When the specification in the datasheet says so, it better be so.

This older question addresses the same problem and the answers confirm what I was thinking, namely that the ESL is determined by the current loop through the capacitor for simple MLCCs.

What the "current loop pictures" implies is 'generally' admissible to begin with, but not as the effective way to arrange "decoupling" cap. Decoupling is needed for the circuit elements that draw current, not for the cap itself.

Which capacitor would have lower ESL and why? + [0603, C1] vs. [1206, C2]

1)) That is apple to orange comparison. :-). 2)) C2 layout, That looks not right, though it is okay. Meantime, effective contact to the "C" (from ESR / ESL) is at the end-cap. Thus, moving the via to the center may not work as wished. It seems 0308 LGA has the contact on the side,not sure how. Otherwise, I imagine that fabrication of "side contact multi layer" would be costly.

While those packages all have roughly the same size, inductance differs by more than an order of magnitude. It suggest that the current loop area is the only (or by far dominant) contribution to the package inductance. Of course, reducing the package dimensions facilitates achieving smaller total loop areas.

When the device manufacturers define ESR/ESL, they are talking about the internal impedance. "Current loop" is a secondary parameter to the manufacturer, that is more on the application side. Thus, the internal impedance does not include the loop (Kelvin point measurement).

If it says so, "order of magnitude difference" might be right, not from the external loop, but from the internal structure.
Hypothetically: Note that ESR/ESL is "effective...". Effective impedance likely become relative to the 'C', and the geometric parameters could contribute by "r^2", while the "order" become major denominator (1/100um vs 1/1um).

However, if this is all there is to it, why do all those guides on decoupling talk about capacitor size so prominently, when it is only a small piece of the whole picture, namely the effort to minimize current loop area? What is the physical reason for MLCC ESL? Is it indeed only the current loop inductance or is there more to it, e.g. some permeability of the capacitor material which of course matters less, the fewer capacitor material there is.

As I explained (trying to sell :-)), "current loop" is at application side. Permeability may affect, but the dominant factor must be from the geometry, internal to the device.