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Usually it is said that small SMD capacitors (e.g. 0603) have lower ESL than larger ones (e.g. 1206). This older question addresses the same problem and the answers confirm what I was thinking, namely that the ESL is determined by the current loop through the capacitor for simple MLCCs.

Now consider the following case of decoupling caps that connect to a power/ground plane pair:

Which capacitor would have lower ESL and why?

enter image description here

Wouldn't the 1206 have lower ESL precisely due to its smaller current loop? Isn't the "capacitor ESL" actually a misnomer because the ESL of the decoupling network is critically caused by its connection to the power rails, i.e. by the number, placement and spacing of the vias rather than the dimension of the capacitor?

The following graphic also seems to suggest that the current loop can be greatly shrunk by placing the vias in tight proximity, because the majority of the current loop is between the vias:

enter image description here

While those packages all have roughly the same size, inductance differs by more than an order of magnitude. It suggest that the current loop area is the only (or by far dominant) contribution to the package inductance. Of course, reducing the package dimensions facilitates achieving smaller total loop areas. However, if this is all there is to it, why do all those guides on decoupling talk about capacitor size so prominently, when it is only a small piece of the whole picture, namely the effort to minimize current loop area? What is the physical reason for MLCC ESL? Is it indeed only the current loop inductance or is there more to it, e.g. some permeability of the capacitor material which of course matters less, the fewer capacitor material there is.

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    \$\begingroup\$ Inductance is caused by current loops so if you can find a clever layout that reduces loop area you can lower inductance regardless of package size. However, the whole current loop counts, not just the part within the footprint, and in practice it will be hard to have an overall smaller loop using larger package in most cases simply because the larger packages take up more space and are harder to route with short traces, especially when many are required. \$\endgroup\$ yesterday
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It’s hard to precisely say here. The thickness of the board relative to the distance between vias can have a meaningful impact on the effective inductance of the double 1206 vias. The construction of the caps might play a small role.

If one made me guess, I’d say the 1206 would be better but if 5 of us who do high frequency layout were at a lunch table, I’d expect a lot of debate and no clear consensus.

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    \$\begingroup\$ Thanks for this answer. Do you mind to add maybe 1 or 2 of the arguments to your answer, that the proponents of either layout would put forth ? ( I know that the 0603 layout is not ideal and I am interested indeed if this bad layout is enough to nullify the advantage that the 0603 might have.) Let's say the two planes are about 0.8 mm deep in the board, i.e. near the center. \$\endgroup\$
    – tobalt
    yesterday
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The current loop area is indeed the main contributor to the overall inductance. The dielectric materials of ceramic capacitors like barium titanate (X5R/X7R) or calcium zirconate (C0G) have basically no impact on inductance.

When you go to a MLCC manufacturers website and estimate the ESL of the actual capacitor e.g. by the self-resonance frequency shown in the impedance plot, you need to consider how the impedance measurement was done. An impedance analyzer with a specific test fixture is used. Compensation and calibration is done using open circuit, short circuit and some specific load. In the process, the inherent inductance of the path length of the cap is compensated out of the system. Take a look at Parasitic Inductance of Multilayer Ceramic Capacitors for more details.

With this information we can take a look at an example of inductances resulting from impedance measurements for different package size 100nF caps: enter image description here Source: Kemet KSIM

So the actual capacitor inductances are in the order of hundreds of picohenry.

What really matters is the total inductance of the current loop which might be in the order of some nanohenry. Now the question is also about pad layout. Lets take a look at a paper from 1999 which shows how the power-plane via placement of an 0805 cap impacts inductance: Pad inductance

You can see that layout is very relevant for the overall inductance. Have a look at the paper ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications for more details.

In essence, the layout is far more relevant for the overall inductance than the actual capacitor. A smaller package of course facilitates a layout with smaller current loops.

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  • \$\begingroup\$ Thanks for the comprehensive answer. I think it addresses pretty much everything I had in mind, with sources for backup. Two questions though: As two close-by vias are basically the tightest arrangement of the current loop through the board thickness, then what is the merit of capacitors that are smaller than 2 vias, so smaller than ~0402. And second. @JRE already posted that AVX link yesterday (deleted) Unfortunately the images are not intelligible. Is the current loop through the fixture comparable for different capacitor sizes or does it not matter due to the calibration? \$\endgroup\$
    – tobalt
    22 hours ago
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    \$\begingroup\$ Smaller components are probably more meaningful in high density designs (smartphones etc.) that also use very small microvias. Second, i assume that manufacturers use calibration/compensation for each capacitors impedance measurement. So the actual loop of the fixture wouldn't matter. \$\endgroup\$ 22 hours ago
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I would vote for 0603 because you can squeeze in two of them in about the same footprint as the 1206, with 4 vias in a criss cross pattern like a poor man's IDC capacitor. This is just handwaving, but it would be interesting to measure it.

enter image description here

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  • \$\begingroup\$ Of course you are right, and you could come even closer to tight power/gnd interleaving with several 0201 caps.. Or with an actual IDC or X2Y cap. The spirit of my question though is what matters more: the actual package size or the via pattern? \$\endgroup\$
    – tobalt
    yesterday
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    \$\begingroup\$ @tobalt In isolation neither matters since inductance is defined over a complete loop and the foot print and vias alone do not form a loop. To understand which is better you need to analyze the complete current loops from the load to the footprint through any bias and then back to the load. Otherwise this is like asking if a 10v power supply is more powerful than a 5v supply without specifying current. The answer could be either. \$\endgroup\$ yesterday
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Usually it is said that small SMD capacitors (e.g. 0603) have lower ESL than larger ones (e.g. 1206).

When the specification in the datasheet says so, it better be so.

This older question addresses the same problem and the answers confirm what I was thinking, namely that the ESL is determined by the current loop through the capacitor for simple MLCCs.

What the "current loop pictures" implies is 'generally' admissible to begin with, but not as the effective way to arrange "decoupling" cap. Decoupling is needed for the circuit elements that draw current, not for the cap itself.

Which capacitor would have lower ESL and why? + [0603, C1] vs. [1206, C2]

1)) That is apple to orange comparison. :-). 2)) C2 layout, That looks not right, though it is okay. Meantime, effective contact to the "C" (from ESR / ESL) is at the end-cap. Thus, moving the via to the center may not work as wished. It seems 0308 LGA has the contact on the side,not sure how. Otherwise, I imagine that fabrication of "side contact multi layer" would be costly.

While those packages all have roughly the same size, inductance differs by more than an order of magnitude. It suggest that the current loop area is the only (or by far dominant) contribution to the package inductance. Of course, reducing the package dimensions facilitates achieving smaller total loop areas.

When the device manufacturers define ESR/ESL, they are talking about the internal impedance. "Current loop" is a secondary parameter to the manufacturer, that is more on the application side. Thus, the internal impedance does not include the loop (Kelvin point measurement).

If it says so, "order of magnitude difference" might be right, not from the external loop, but from the internal structure.
Hypothetically: Note that ESR/ESL is "effective...". Effective impedance likely become relative to the 'C', and the geometric parameters could contribute by "r^2", while the "order" become major denominator (1/100um vs 1/1um).

However, if this is all there is to it, why do all those guides on decoupling talk about capacitor size so prominently, when it is only a small piece of the whole picture, namely the effort to minimize current loop area? What is the physical reason for MLCC ESL? Is it indeed only the current loop inductance or is there more to it, e.g. some permeability of the capacitor material which of course matters less, the fewer capacitor material there is.

As I explained (trying to sell :-)), "current loop" is at application side. Permeability may affect, but the dominant factor must be from the geometry, internal to the device.

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