I'm trying to do the most basic of Verilog "Hello, World" examples and can't figure out why this won't work:

module bkg(a,c);
  input a;
  output c;
  assign c=a;

Driven with:

  reg x;
  wire z;
  bkg BKG(.a(x),.c(z));


The result here is:


No matter what the input is, the output is always x. If I changed the assignment to a constant (rather than the input) like assign c=0; - the output is expectedly 0.

I've read up on wires vs reg and continuous assignment, etc. - Can't figure out what I'm missing!

  • 3
    \$\begingroup\$ Try adding a small delay after x=1; \$\endgroup\$
    – Eugene Sh.
  • 2
    \$\begingroup\$ Using x and z as identifiers in verilog is a really bad idea. \$\endgroup\$ yesterday

You might need an initial block to monitor the signals x and z and display them when any of them changes:

initial begin
   x = 1 ;
   $monitor("x = %0x, z = %0x", x, z) ;

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