I'm trying to do the most basic of Verilog "Hello, World" examples and can't figure out why this won't work:
module bkg(a,c); input a; output c; assign c=a; endmodule
reg x; wire z; bkg BKG(.a(x),.c(z)); x=1; $display(x,z);
The result here is:
No matter what the input is, the output is always
x. If I changed the assignment to a constant (rather than the input) like
assign c=0; - the output is expectedly
I've read up on wires vs reg and continuous assignment, etc. - Can't figure out what I'm missing!