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I have a problem identifying an error in the code for the inputs of a comparator. It shows the error:

Error (10170): Verilog HDL syntax error at assg_verilogq2.v(2) near text: "input"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

The code that I wrote is:

input [3:0]x,y;

the full code

module FA2(x,y,ci,co,V,N,Z);

input [3:0]x,y;
input ci;
output co,V,N,Z;

wire [3:0]a,s;
wire [3:1]c;

assign a = ~y;
assign V = co^c[3];
assign N = s[3];
assign Z = ~(s[3]|s[2]|s[1]|s[0]);

FA P0(x[0],a[0],ci,c[1],s[0]);
FA P1(x[1],a[1],c[1],c[2],s[1]);
FA P2(x[2],a[2],c[2],c[3],s[2]);
FA P3(x[3],a[3],c[3],co,s[3]);

endmodule

Does anyone know this error?

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    \$\begingroup\$ I think you should post the full code. Problem could be rooting from somewhere else. \$\endgroup\$
    – Mitu Raj
    yesterday
  • 2
    \$\begingroup\$ Your error message indicates the error is on line 2, but the code you show input is on line 3. \$\endgroup\$
    – dave_59
    16 hours ago

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