My goal is to disconnect the battery while the device is connected to USB Input. However when the device is disconnected from USB power, the battery will be connected to the system load.

I am using back-to-back NMOS transistors with gate connected to USB power to turn on the lipo charger when the device is plugged in to USB. When USB power rail is low, the NMOS transistors should block current.

I am trying to achieve the opposite effect with the connection of the battery to the load with back-to-back PMOS transistors.

The diode is intended to prevent the battery from turning the NMOS transistors back on.

My two questions:

  1. Will this work in theory assuming I select appropriate transistors? I'm not doing anything stupid right?

  2. Is the pull down resistor necessary for the PMOS transistors?

Thanks, this is my first post so go easy on me.

Circuit Diagram

  • \$\begingroup\$ Easy, use a simulator to prove your idea out then, you might be able to see that dual back to back MOSFET s are probably not required unless you have withheld something. \$\endgroup\$
    – Andy aka
    Commented Nov 26, 2021 at 19:48
  • \$\begingroup\$ Trying to disconnect USB power from charger does not make any sense to me. If USB is not connected then it is not... well, connected, anyway. On the other hand, disconnecting the battery from system when USB power available is a good idea, because system load will not affect charging profile. But you do not have to implement power path by yourself, unless you want it as an exercise. Battery chargers with built in power path are available nowadays. They also usually include ideal diodes, unlike your SS54 with 0.5V drop. \$\endgroup\$
    – Maple
    Commented Nov 26, 2021 at 22:49
  • \$\begingroup\$ Thank you very much \$\endgroup\$
    – I_LIKE_JAM
    Commented Nov 27, 2021 at 10:42

1 Answer 1


For full enhancement and minimum Rdson ("saturation"), most power MOSFET's are specified at Vgs = 10 V. Logic level FETs are spec'd at lower Vgs, such as 5 V. In your circuit, the drive voltage for M1 and M3 is nowhere near this. Assume both FETs are ON, write the circuit voltage at each of the six pins on the drawing, and see if the required conditions are met.

For high-side switching with an n-channel FET, the gate has to be 5 V or 10 V above the input voltage being switched. This is why most high-side power switch applications use p-channel FETs. Linear Technology, Maxim, and others make high-side driver chips with an onboard charge pump produce the required gate voltage.


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