I just started to learn Verilog in college so please forgive me if this is an elementary question. I know there can be multiple modules in one .sv file. But in that case, what is the naming convention for that file? For example, if I have a Verilog file with module Test1 and Test2, what should I name this .sv file? Because normally when the professor demonstrates writing Verilog there is only one module in each file so he just uses the module name for the file name.
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3\$\begingroup\$ Put any name as required by the company you work for / your course work. For eg: same name as the module. \$\endgroup\$– Mitu RajCommented Nov 27, 2021 at 0:08
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Most Verilog compilers have an automatic search capability that look for modules that you have instantiated but have not compiled yet. It will take the name of the module and append .v to the filename for Verilog files and .sv for SystemVerilog file. Then search through specified directories for that filename. You do need to be careful of file compilation order dependancies with timescales and macros.
Whether you use that capability or not, it is a good file naming convention.
