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This is my first time diving into DC/DC converters, so I'm learning a lot of new information and am aware that I may miss some important details. I'm hoping that others with more experience could point out and educate me about those, why they are crucial, and what they cause.

A little bit about the circuit

My input voltage is around 5V (I put 4.5 to 5.5V in the TI designer), with an output of a little over 3.3V. The expected load of the powered circuit is around 800mA, worst-case about 1.4A for a few minutes. For this purpose, I chose TI's LM2831XMF/NOPB (mostly because it was one of the only available 1.5A DC/DC converters I could find in stock near where I live due to chip shortage). I changed some of the components from the original "compact" design provided by TI's generator, like the inductor (IHLP1212BZER3R3M11) and the "drain" diode (SL04-HE3-08), which should be decent replacements for the suggested parts.

The schematic

This is the schematic I came up with at the end:

Schematic

The PCB

The board I use has 4 layers. The red layer is the top layer, lower I have a ground layer followed by a VCC layer and the bottom layer. I try to provide a good ground for the output capacitor, diode and input capacitor (like suggested in the switching chip datasheet). I also put big pours as traces to reduce resistance between parts. Furthermore, I tried to reduce both fill and drain loops as much as possible, so this is the layout I came up with at the end:

PCB

Without copper pour for better visibility:

No pour

My existing concerns

What I'm worried about the most here is the feedback line, which I routed not that far from the inductor and could potentially cause output ripple. Would it be better to route it around the other side (to avoid the inductor more)? Doing that, I'm worried I'll make it into an even bigger antenna and worsen the situation. Do you perhaps have any suggestions on how to fix/deal with such an issue, or is it a non-issue as-is?

The solution:

This is the final design (imgur.com) I'll use in production. I'll also update with some ripple data once I get the circuit and assemble the regulator.

Update: this design produces under somewhere around 5 mV of ripple, which should be good enough for most designs.

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    \$\begingroup\$ On our evaluation kits, we usually route the feedback trace on layer 4, with unbroken groundplane on layer 2 to help shield the feedback input from switching noise. \$\endgroup\$
    – MarkU
    Nov 26, 2021 at 22:50
  • \$\begingroup\$ @MarkU Didn't think it's okay to route it through VIAs, as it passes multiple layers doing so (and they may act as additional antennas). Thank you for the suggestion, might go with that if nothing "cleaner" turns out to be the solution \$\endgroup\$
    – Mysterious Wolf
    Nov 26, 2021 at 23:02
  • \$\begingroup\$ Routing through vias is usually fine. The coupling between a plane and a wire perpendicular to that plane is very small. (note that via is not an acronym, and does not need to be capitalized!) \$\endgroup\$
    – Hearth
    Nov 26, 2021 at 23:28
  • \$\begingroup\$ If you want a cooler layout more copper area is needed. TI suggests this i.stack.imgur.com/sgm87.png \$\endgroup\$
    – Tony Stewart EE75
    Nov 27, 2021 at 0:31
  • \$\begingroup\$ @TonyStewartEE75 Where did you find that? Other than pouring a year worth of copper production on the board, that layout breaks just about every guideline from the their datasheet \$\endgroup\$
    – Maple
    Nov 27, 2021 at 1:05

1 Answer 1

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The SW copper pour sticks out too much beyond L1 pin. This does not improve current carrying capacity much but increases noise.

The footprints for capacitors look rather small. Did you cut the voltage rating too close?

But the biggest problem is that C7 is way too far from GND pin of U1 and connected to it through two sets of VIAs. I recommend moving it closer and connect via uninterrupted GND pour. Something like this, perhaps?

enter image description here

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  • \$\begingroup\$ Thank you for the suggestions - much appreciated. The input capacitor is rated at 35V, while the output capacitor is 6.3V (both in a 0603 package). Is this not enough? As for the vias, they look much smaller on your suggested design than what I have (12mil hole, 24mil pad). Would you suggest I reduce their size and put more of them to increase the total surface area of copper through the board? \$\endgroup\$
    – Mysterious Wolf
    Nov 27, 2021 at 8:31
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    \$\begingroup\$ The capacitor ratings are OK. The suggested design was made in 5 min with Photoshop only as an example of compact layout that follows all datasheet guidelines and optimizes traces. It can be used even with single layer PCB and it allows good thermal dissipation by either expanding GND and VIN zones or by stitching them to other layers right next to chip pins. But the component dimensions could be all wrong, so do not take it as an actual layout. I am also using 0.3mm VIAs, but I haven't done any comparative calculations. Don't think going under 0.2mm would be any better. \$\endgroup\$
    – Maple
    Nov 27, 2021 at 9:45
  • \$\begingroup\$ This is the design I derived from yours now: imgur.com/a/Q8H9WBs The only major difference is that there are a few more ground vias in the middle and that I put the output capacitor sideways to shorten some connections (could this perhaps cause issues when put near the inductor?) \$\endgroup\$
    – Mysterious Wolf
    Nov 27, 2021 at 9:57
  • \$\begingroup\$ Looks very good. I would push R8, C9 a bit down, and put D3 closer to the chip. You will lose 2 top VIAs , but the SW zone will be smaller and you can compensate by adding Vias next to Vin pin, since you passing Vin to another layer anyway, just further on the right. Also you can move C7 closer to SW pin. \$\endgroup\$
    – Maple
    Nov 27, 2021 at 10:13
  • \$\begingroup\$ One useful trick for maximizing heat dissipation is to draw all other zones with higher priority, then draw GND zone with lower priority and a bit of overlap. This way it will expand as much as configured clearance allows. But you seem to be doing exactly this already. \$\endgroup\$
    – Maple
    Nov 27, 2021 at 10:18

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