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Our PCB manufacturer specifies that there should be a minimum clearance between holes of 0.5mm when nets are different.

I am getting a lot of errors when I have thermal pads with embedded vias closer than 0.5mm, but the nets are all GND. How can I create a rule that only applies to vias that are NOT of the same net?

I can see that in Design -> Rules -> Manufacturing -> Hole To Hole Clearance, I have the ability to make custom queries for each entity but I dont see how to trigger a violation based on their equivalency.

Thanks for any advice.

EDIT: Its not just GND nets, there are other instances too like the following pads with integrated vias. They are closer than 0.5 to the oblong slot but not enough to cause manufacturing issues. enter image description here

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    \$\begingroup\$ How many nets are impacted? if it's just the ground net then making a rule that just applied to the ground net might be an option. \$\endgroup\$
    – Peter Green
    Commented Nov 27, 2021 at 1:51
  • \$\begingroup\$ altium.com/documentation/altium-designer/… \$\endgroup\$
    – Mitu Raj
    Commented Nov 27, 2021 at 2:24
  • \$\begingroup\$ @PeterGreen Thanks for the comment, but there are other nets too, see edits. \$\endgroup\$
    – TripleAntigen
    Commented Nov 27, 2021 at 3:07

1 Answer 1

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Please see: https://bugcrunch.live.altium.com/#/idea/17603

For a requested Altium Designer feature (idea). It also lists some helpful work-arounds for the meantime.

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    \$\begingroup\$ Please put relevant information in the post so if the link goes down the answer is still valid \$\endgroup\$
    – Voltage Spike ♦
    Commented Jul 10 at 21:04
  • \$\begingroup\$ The link is to bugcrunch which is behind login barriers. Doesn't work without an altium account. \$\endgroup\$
    – MrGerber
    Commented Jul 11 at 5:55

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