What are the risks of having a small annular ring?

Question

I want to increase the hole size of my signal vias on my PCB from 8mil to 12mil since that will save me about $100 getting the boards manufactured.

I increased the hole size, but for now, I left the via diameter as-is (which is 16mil). The general practice that I follow is that the via diameter should be 2x larger than the hole size. Increasing the diameter to 24mil would be difficult, since it would require some extra time to move components around on the board.

So my question is: what are the risks of having a via diameter that is too close to the via hole size?

Answer 1

The ability of the manufacturer to center the holes on the copper pattern varies with their equipment and skill level and the trade-offs they make in their processes to get productivity vs. extremes of accuracy.

Here is a typical "capabilities" entry (Pcbway):

And another (Sunstone), there are two given, the one on the right will likely add to the cost:

And yet another (Twisted Traces)

And yet another (JLCpcb)

If you allow 0.15mm then all but one of the manufacturers shown here can handle the work without charging more (assuming 1oz copper). That means a minimum pad diameter of about 24 mils.

If you submit a job which does not meet their advertised capabilities, there are several possible outcomes:

• They will try to manufacture the board (silently) and may have some pads that are so far off center than they break through the edge. This is probably the worst outcome, since it may be okay one one order and not the next, or some boards may be okay and some may not. Their design rule checking software should reject the files but a cheap protoboard maker may not always do so.

• They will reject files and send them back for you to fix them

• They will quote a higher price to try to manufacture the boards from the files as given.

I suggest canvassing your potential supplier list (usually their websites will have the information) for their minimum annular ring capability and setting this in your own EDA design rule checking default. Same with the minimum drill size. That way you won't accidentally spend a lot of time designing a board that can't be easily manufactured, or alternatively you will make the conscious decision to go to a more expensive process in order to get things to fit. Rules when you are using HDI are, naturally, much tighter, with as low as 60\$ \mu\$m annular ring just possible (for a price).

Answer 2

NOTE: 1 mil = 0.001 inch which is 25.4 microns.

So you have a 16 mil pad with a 12 mil hole in it. This means there is a 2 mil ring of copper all around the hole IF the hole is perfectly centered.

If the hole location is off by 2 mils (compared to pad), you will have a tangency (edge of hole coincides with edge of pad).

If the hole location is off by more than 2 mils, you will have a breakout (hole extends beyond border of pad).

When the hole extends to or beyond the edge of the pad, this creates problems during the drilling and/or plating process, and can lead to metal slivers or shorts. Normally board fabricators will not allow this.

So the question becomes, how accurately can the fab house drill the holes? If they can hold to a tolerance of +/- 1 mil, maybe it is OK, because you will still have 1 mil of annular ring in this case.

Ultimately the board house should be able to tell you whether these vias are OK. My guess is that you need to enlarge the pad at least a little bit but it is worth asking the question.

Answer 3

The problem you could run into is the drill could cut the track as there is limit on the precision.

Take this case. Drill hit is perfectly in the centre, and the etching is equally perfect. Everything looks good

Take this instance where the drill centre is off. It is still electrically connected to the trace but there could be impedance changes due to this

In this instance the track is completely cut off. Now this can be mitigated via teardrops to increase the area around where the trace connects, but fundamentally if the annular ring is below the fabricators limit there is a increase chance of fabrication issues and there will be technical reasons that the fabricator set these limits

Answer 4

There are three reasons I try not to push annular rings to the limits.

1. Hole placement (drill registration to top metal layer) to make sure the via is well centered. This is primarily a reliability concern but can be a concern at high speeds for other reasons.

2. Ensuring a good "wrap" between the via and top metal. This is required for reliable via connection after thermal cycling. In some fab processes, the via and the top pad are one metal deposition process. In others, the top pad is created in a separate step creating what's called a "butt joint". The real requirement depend on many factors such as CTE of the dielectrics, number of layers, metal thickness, etc. But generally a minimum of 1 mil is required (after all manuf tolerances)

3. When the limits are pushed in one area, the fab house has to pay attention to it, and may not pay as much attention to other factors I care about more. I generally try to design to the limits only where I really need it.

I try to use a 6mil annular ring (as drawn) in my PCB layout, but use a 4mil in some cases (25GHz high speed lines for example).

Answer 5

You need to design a large enough ring around the hole so that they can get the hole inside the ring when they drill the hole, the order form with the prices will tell you how big you must make the annular ring.