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I'm trying to implement a Dadda tree multiplier in SystemVerilog using generate blocks. However, the algorithm I'm using to instantiate the logic requires arrays, and the genvar type does not seem to support arrays. In theory, I could use some external script to produce the required Verilog code, but that would be difficult to write and verify.

As part of the Dadda tree algorithm, I have to keep track of the heights of each partial sum column. For example, here is the first part of the algorithm:

logic [62:0][31:0] products[STAGES];

genvar i, j;
// Heights of each partial sum column
genvar colHeights[STAGES][63:0]; // syntax error

generate
    // Record all the initial products
    for (i = 0; i < 32; i++) begin : a_loop
        for (j = 0; j < 32; j++) begin : b_loop
            assign products[0][i+j][colHeights[0][i+j]] = a[i] & b[j];
            colHeights[0][i+j] = colHeights[0][i+j] + 1;
        end
    end

    // ...
endgenerate

colHeights is supposed to be a multidimensional array, but my compiler does not seem to recognize that.

Is there a way to create arrays which can be read from and written to during module instantiation? If not, is there another way I can instantiate modules based on the results of an algorithm like this?

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    \$\begingroup\$ A genvar is just a loop iterator that gets unrolled into a constant at compilation. It is not a variable. You need to explain what kind of array you want; an array of wires, variables, or module instantiations. It might help to show a piece of code without using generate that manually describes what you want to do. \$\endgroup\$
    – dave_59
    Nov 28, 2021 at 3:39
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    \$\begingroup\$ At some point, it may become useful to use a more general-purpose language (e.g., Python) to generate the structures you want. \$\endgroup\$
    – Dave Tweed
    Nov 28, 2021 at 4:47
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    \$\begingroup\$ Sounds like an XY problem to me. Describe your problem first, not the attempted solution. \$\endgroup\$
    – Mitu Raj
    Nov 28, 2021 at 5:22
  • \$\begingroup\$ Does this answer your question? How to create a nested for-loop in Verilog? \$\endgroup\$
    – devnull
    Nov 28, 2021 at 12:03
  • \$\begingroup\$ I added some details about the kind of algorithm I'm looking for. \$\endgroup\$
    – Woofmao
    Nov 28, 2021 at 20:05

1 Answer 1

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There is no need for colHeights to be declared as a genvar. You can declare it the same way as you are declaring products (that is, as a logic array), and write and read it inside the generate loops. As long as you avoid writing to the same slice in multiple iterations, there will be no multiple driver issues.

A genvar has a single purpose only, which is to use as a generate loop iterator. I prefer to put the declaration inside the for-statement, like this:

for (genvar i = 0; i < 32; i++) begin : a_loop
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  • \$\begingroup\$ colHeights is never accessed after instantiation, but it needs to be read and written multiple times during instantiation. I'm looking for an array type that can be used before module instantiation. \$\endgroup\$
    – Woofmao
    Dec 1, 2021 at 22:48
  • \$\begingroup\$ I don't understand what you mean by that. What I can tell you is that genvar is not what you are looking for, because the only legal use for genvar is generate loop iterators. If you are looking to conditionally instantiate modules inside your loop, perhaps you could write a function, and call that function in a generate-if? \$\endgroup\$
    – pc3e
    Dec 2, 2021 at 14:32

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