# Low performance in the MC34063 chip. Wrong BJT voltages, out of spec timings - how not to trust a datasheet

EDIT at the bottom.

Referring to a previous question which I solved, it was related to a inverting boost configuration of the MC34063 with the following arrangement:

Picture 1

I realized my circuit and calculations were right, and the question was solved. What remained open, though, was another issue: why from the measurements the Vsat of the internal switch was 1.6V or so, while by following the components selection, it should still be in the range of less than 0.5V (from datasheet).

To recap the component selection:

• R1 = 0.33 Ohm
• C1 = 47μF (electrolytic)
• R2 = 49.5 kOhm
• R3 = 2.49 kOhm
• C3 = 680 pF
• D1 = V4PAN50-M3/I
• L1 = SRN1060-221M
• C6 = 47μF (electrolytic)

I had the correct 50mA at the minimum input voltage of 6.5V, obtainable from the following formula:

$$\ \frac{t_{on}}{t_{off}} = \frac{|{V_o}| + V_{diode}}{V_{in}-V_{sat}} \$$

Measuring the on/off time ratio at the worse case scenario of the minimum input voltage with the maximum load (50mA), I discover that the minimum input voltage is 6.5V, since the on/off time ratio is 5.2 and the Vsat is 1.6V. Putting values in the formula will actually verify what is happening.

My question is why the chip keeps an on/off time ratio close to the minimum in the datasheet with all the 6 parts I tried, and why the Vsat is so high (way out of spec).

This is the scope acquisition of the pin 3 on channel 1 (timing capacitor) and the pin 2 on channel 2:

Picture 2

And here on channel 2 and 4 are, respectively, the pin 2 and the pin 1 (shorted with 7 and 8), showing the input voltage at around 6.5V (on the acquisition is lower at 6.1V though...), and during on-time the inductor voltage is around 4.5V, see acquisition:

Picture 3

The acquisition is taken with a light load, as you can see the inductor current goes to zero and voltage oscillate at a certain resonant frequency before decaying to zero.

Is there anything obvious here?

EDIT:

• There was a complain about not having the original schematic that I have used, so here it is.
• Also, in an answer I've been pointed out that the max Vce sat is 1.3V, while I wan mentioning it was 0.5V. Indeed I was wrong, but is also important to mention that this still does not explain my reading of 1.6V which is above the absolute maximum.
• A scope acquisition was not convincing, so since I have no access to it now, I will update with a better one a bit later.

EDIT 1:

• Scope acquisition updated posted in this EDIT1:

Picture 4

The natural ringing of the oscillator now shows that there is no fundamental error in my setup/calibration.

The open question, considering the observations I received of the Vce_sat, is the following:

Why the V_ce stays around the maximum value from the datasheet (max 1.3V, measured 1.6V), far from the typical? And, from previous question, why the t_on/t_off ratio stays around the minimum value of 5.27, where minimum is 5.2? Is this related somehow? Did I missed something else?

I just wonder if someone else had a similar issue with similar specs. I am using a PCB I designed. As I have no problems in posting the grounding of the top of the test board I made (the bottom is just an entire GND plane), and also a 3D view, I hope I can provide some more insights now:

Also, the effectively mounted component, are the one shown in the initial schematic.

Picture 5 Picture 6

• When you show a circuit diagram it trumps words. When you then use words to give new values of components already placed in that schematic, you do the reader a disservice. Use your favourite picture editor and update the circuit and throw away the words that attempt (rather poorly) to do the same. Simplify for the reader and put notes in the diagram about the load resistance. Be specific and don't ask people to guess. Nov 28 '21 at 22:02
• Are you sure your scope is properly calibrated? Perhaps one of the channels has a bit of a voltage offset, making the calculated difference incorrect. Try connecting both channels to pin 1 and see if you get a zero difference. Nov 29 '21 at 7:55
• Regarding the schematic, I really hope it will help more with the new update. @TooTea I will put a more complete acquisition soon. Dec 2 '21 at 9:56
• I can't make sense of the scope shots, which color is which pin? Dec 19 '21 at 20:48
• @bobflux I edited with the specified channel associated to the relative pin - forgot that for the first picture! Dec 19 '21 at 22:32

A short verification simulation using LTSpice and the MC33063A model from http://ltwiki.org/index.php?title=Simulating_the_MC34063_in_Inverter_Configuration_with_an_Accurate_TL431A_Model yields the following behavior (one has to remove the I2 declaration below the "force f/f reset at startup" comment in the model):

Simulation result for shown circuit. Shown are the voltage before (green) and after (blue) the transistor.

This is in a good agreement with the captured curves. A short inspection shows the current through R3 and the voltage drop between Pin 1,7,8 and 2 according to the simulation.

So what is going on? Well a short search yields that some datasheet actually show the following curve:

This looks like the observed behaviour. A closer look to the specs reveals that they actually "cheat" a bit: they show the CE of the separate stages. You have to add both to get the actual relevant total CE.

EDIT: to add on the $$\\frac{t_{on}}{t_{off}}\$$ question - as observed in the simulation $$\I_{pk}\$$ is around 330 mA for an one ohm voltage supply. Assuming an output load current $$\I_o\$$ of 25 mA one gets $$I_{pk} = 2 I_o \cdot \left(\frac{t_{on}}{t_{off}}+ 1 \right) \\ => \frac{I_{pk}}{2 I_o} - 1 =\frac{t_{on}}{t_{off}} = \frac{|V_o| + V_F}{V_{in} - V_{sat}} => |V_o| = \left(\frac{I_{pk}}{2 I_o} - 1 \right) \cdot (V_{in} - V_{sat}) - V_F \\ \approx \left(\frac{330 mA}{2 \cdot 25 mA} - 1 \right) \cdot (6.3 V - 1.5 V ) - 0.4 V \approx 27 V$$ This is already pretty close the target voltage. One will notice that most parameters like $$\V_F\$$ and $$\V_{sat}\$$ are actually depending on the current. Actually $$\I_{pk}\$$ goes down while approaching the theoretical maximum voltage limit and depends on the on time. For longer periods the current can ramp up more allowing for higher voltages or output currents. For details I recommend setting up the simulation.

EDIT2: The ratio $$\\frac{t_{on}}{t_{off}}\$$ is defined by ratio $$\\frac{I_{dischg}}{I_{chg}}\$$ if no inbetween reset is triggered e.g. if the target voltage is reached. So looking into the charge current of C2 we see:

Current over C2. First marker line at 43.5 µA, second marker at -206.9 µA.

Checking the datasheet, one notice that the charge current is "too high", resulting in a low ratio. A short look into the model reveals that the bias current of 35 µA is accompanied by a leakage current of ~ 10 µA over S3. If Roff is changed to e.g. 1e17 the ratio goes up and the circuit works as "expected". Same goes if the difference between VCC and the target voltage is reduced i.e. target voltage lowered.

TL;DR: everything seems to work fine and within specs/model. One just have to interpret them in the intended way and mind their finite limitations.

• In this datasheet (onsemi.com/pdf/datasheet/mc34063a-d.pdf) you show the Fig. 5. There is also Vce in Fig.6 - does that mean that my configurations has the conditions of Fig. 5? For the rest, is a great simulation, thanks for that. Dec 23 '21 at 15:29
• Because interestingly, I measure a 1.6V of saturation, which happens, according to the graph, at a peak of 0.9A, although it does not reach it: the ton/toff impedes the inductor to charge at such current. With your formula you are showing that what happens makes sense according to ton/toff, and we are limited by this value that limits the peak current, therefore the output power (I and/or V). But the problem is that the logic won't allow a longer ton/toff, and this depends from the oscillator - this I cannot explain. How behaves your simulation with an input of 4.5V? Dec 23 '21 at 15:42
• (Input voltage at output loads from 25mA to 50mA - if your model is like the real part, the ton/toff will not allow you to reach the full -25V @50mA, not even 25mA --> but according on the ratio in the datasheet, -IT SHOULD-) That is the mistery to me, the second half of the mistery, worth to say Dec 23 '21 at 15:50
• I will simulate. It will proof you answer on the Vce, although cannot give explanations on the timing ratio not met. BUT, i might be that I did not achieved the maximum ton/toff because of the reset issued from the drop on the 0.33 resistor. Meaning I have to check against the simulation if I was reaching peaks earlier (then why?). Not to mention tolerances on the comparator in the timing circuit. But the calculations were showing was possible to achieve -25V, with peak current 0.9A (4.5V). Using worse case scenarios did not change so much as I see in reality. Dec 23 '21 at 22:49
• small addition: reason why Vce drop is >1.4 V is that the base and the collector share the same voltage source which implies that 2 *Vbthreshold must be taken into acount. Below that threshold no significant current will flow. Dec 24 '21 at 15:11

I honestly haven't studied your scope outputs. (I apologize for that, as I'm glad you added them, regardless.) But I did do a quick check for obvious thoughts. And I have one for you.

This MC34063A datasheet shows the following:

You write:

it should still be in the range of less than 0.5V (from datasheet).

Note the specifications when pins 1 and 8 are connected, as you show them in your schematic.

What are the specifications shown there?

• And this is why we don't use BJTs for power electronics anymore. Nov 29 '21 at 1:00
• This doesn't really say why the measured Vce is more than 1.6 V when the specs say 1.3 V max, 1 V typical. That's still a huge difference. Nov 29 '21 at 7:48
• @TooTea Agreed! However, the OP make an incorrect statement. Also, the specification provides values that are much closer to observation. This still means there is a residual difference to explain. But the OP also asked for *"anything obvious here?" And I provided at least one step in the right direction, there.
– jonk
Nov 29 '21 at 7:56
• Indeed I oversee this spec (actually, more forgotten...) but as mentioned, I am still out of the maximum spec. Just wondering, before providing better acquisitions, is the way I measured the Vce sat correct? Dec 2 '21 at 9:59
• @thexeno Hmm. I just attempted to read more of that answer. The writer appears to suggest that the simulation model itself includes an S3 switch-off impedance that is "leaky." Assuming the model is a good representation of the internal switch, then the writer further suggests that this leakage explains the timing difference between the expected and actual results -- as the writer modified the model to remove the effect and the timing came out much closer to the predicted value. Is that your reading, too?
– jonk
Dec 24 '21 at 21:24

You are using the Darlington connection for the device. Therefore the relevant spec is 1.3 V.

This spec is for the voltage between pins (1 and 8) and pin2. Your scope shot shows the V on VCC and pin 2; you are ignoring the I*R drop on the 0.3 Ω, and don't show the current.

Use the scope to display pins 1 and 2 simultaneously.

(Also - do you have genuine parts ?- from a reputable distributor ?)

You are not measuring the saturation voltage of the driver -- you are measuring the V between pins 1 (&8) and 2. However this Darlington is driven from VCC (pin 6), and the voltage at pin 2 (switch emitter) is defined by the drop of the internal driver (say 0.3 VCE_sat of a PNP) plus the VBE of each NPN in the switch (say 0.7 V each) -- for a total of 1.7 V.

You 'gain' some saturation measurement by the 0.3 Ω -- basically this doesn't affect the voltage on pin 2 until the switch output transistors saturate (at ~ V(8,2) = 1.3 V). Basically you could increase R1 with no effect on V(6) until those transistors saturate.

• Hi, in the third picture, "channel 2 and 4 are the pin 1 and the pin 2". the EDIT was basically showing the same acquisition, but showing also that the ringing was going back to zero - since this was addressed in a comment as a potential error in my scope. So I am measuring after the 0.3 Ohm. You can also notice the slope due to the current increase in the inductor. Dec 19 '21 at 17:45
• The parts were from Mouser. I thought could be hand soldering, but the big issues I saw were only with high precision parts that loose some precision, i.e. calibrated gm in a current sense device showing different gain - although still in range. Dec 19 '21 at 17:50
• FYI - I reverted a description in two acquisitions, now is corrected, my apologies. Although your answer remains relevant, irrespective to the correction. Dec 19 '21 at 23:13
• fundamentally, you are not measuring VCE_SAT in this configuration since the voltage drop between pins 6 and 2,5 is VCE_SAT of an internal PNP plus 2 VBEs of the main switch. The voltage between 1,7,8 and 2,5 is just this above value minus the I*R drop across the 0.3 Ω. This is not the limiting VCE_SAT. You can only observe VCE_SAT with this IC using a boost configuration, or some more complex driver circuits. Dec 19 '21 at 23:26
• VCE_SAT is when the base current * beta exceeds the collector current (which would be externally limited). In the emitter-follower configuration you are using the switch with, this is not the case. You are measuring VCE, not VCE_SAT. This VCE is controlled by the VBE of the 2 transistors plus the VCE_SAT of the internal PNP driver. Dec 23 '21 at 16:20

Tony Stewart provided the answer already: the Ic current controls the Vce value. The Vce SAT is not a carve in stone value. It varies depending on the collector current controlled by the load (in your case the inductor current of 900mA). What the Vce SAT in the specs means is that this is the value when for a very small change in the collector current there is a major change in the Vce voltage as opposed to below the Vce SAT when a major change in the collector current cause a minor change in the Vce voltage. So, for a load current (inductor current) of 900mA the Vce is 1.6 volts as per Figure 4. Emitter Follower Configuration Output of the data sheet. The following video https://m.youtube.com/watch?v=fqeUpATJlZY presents a technique that uses the Vce voltage specifically to control the current limit of a circuit (like an electronic circuit breaker). It provides several experimental results showing how the Vce changes as the collector current changes, for different base current.

Why (does) V_ce stay around the maximum value from the datasheet (max 1.3V, measured 1.6V), far from the typical?

Fundamental to all transistors as "switches" is that they have bulk resistance and hFE or Beta must be over-driven to 10% of the maximum linear value in order to reach the rated Vce=Vce(sat) @ Isat.

This is self-evident by the slope $$\ R_{CE}=\dfrac{V_{CE_{(sat)}}}{I_C}\$$of Figures 5 and 6 from the pdf file below it.

Using the left plot.

Thus looking at the current loop we can simplify it as follows;

simulate this circuit – Schematic created using CircuitLab

The Ic current controls the Vce value, which you can measure with a 10:1 probe (tip & ring and no grd clip) on a 10 mohm shunt on 0V=Gnd with lead lengths < 1cm (10nH).

If your problem is transformer saturation measuring current only the way I descibed will reveal the problem. This may reduce parasitic issues with your measurement methods.