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I need to make a circuit with an opamp and passive components that has those constraints :

  • When it receives a pulse on one input, its output should be high.
  • After a predefined duration T, it should switch back to low state
  • If a second pulse is received while the output is still high, the duration before the switch should be reset back to T

In a nutshell, it should behave kind of like a watchdog timer but made with passives and an opamp, as I can't use an IC with this precise function because of contraints on the components I can use.

I have already tried this:

Circuit already tried

When it receives a pulse on the positive input, the output will be high while the voltage on the negative input is lower than half (R89 / (R88 + R89)) the output voltage. The main problem is that the circuit is not really reset when another pulse occurs, which means the output will be switched low regularly, even if the timer should be reset:

Graph

Do you have any idea either how to improve the circuit, or of another one to achieve the same goal?

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    \$\begingroup\$ An op-amp is (almost always) an IC. So why do you say you cannot use an IC? \$\endgroup\$ Nov 29 '21 at 13:00
  • \$\begingroup\$ I think you've already come across the main problem of the circuit : memory. You're gonna have a hard time introducing the third requirement without the means to retain the state for at least T, so that you may reset the "circuit state" by a second pulse before T expires. If a second IC can be used you may look into a D-latch with CLR and set functions that may allow you to retain the state for at least T, so that you may be able to clear it before T... \$\endgroup\$
    – citizen
    Nov 29 '21 at 13:10
  • \$\begingroup\$ @MathKeepsMeBusy I did not express myself well, I wanted to say a watchdog timer IC or something like this, because I have constraints on what components to use. I will edit my question accordingly \$\endgroup\$
    – charon25
    Nov 29 '21 at 13:10
  • \$\begingroup\$ Why do you have these constraints? Is it because it's a homework question (if so it should have a homework tag)? What about using transistors? \$\endgroup\$ Nov 29 '21 at 13:12
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    \$\begingroup\$ See if this maybe adapted to your requirements : edn.com/use-an-op-amp-as-a-set-reset-flip-flop \$\endgroup\$
    – citizen
    Nov 29 '21 at 13:24
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Just raw schematic to show principle.

C1 is initially charged, after trigger pulse come the SR is set (Q=1) and the C1 is discharged through Q1. Once the trigger pulse disappear the C1 starts charging and after T resets the output of SR (Q=0).

You must ensure the trigger pulse is long enough to completely discharge the C1.

schematic

simulate this circuit – Schematic created using CircuitLab

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You could do something like this (time constants can be modified to your needs). The parts in the dashed box are needed if you want to prevent a constant high level from driving the output high.

This circuit also produces a high pulse at power-up. By flipping some parts that can be avoided if you require it.

schematic

simulate this circuit – Schematic created using CircuitLab

As shown, one the rising edge of In, current flows into the transistor base and resets C1 to within tens of mV of 0V. When In goes low, C2 discharges through D1. C1 charges through R1 and after about one time constant the output goes low.

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What you have is a monostable multivibrator, but what you want is a retriggerable monostable. A search for that term will kick up hundreds of schematics, and you should be able to see a common pattern in many of them.

Does the input signal have to be positive-going, or can you declare it to be negative-going?

Because your question doesn't put any constraints on the available input signal current, consider C79 to the input, where it is instantly recharged whenever the input signal goes high.

UPDATE:

Now that we have more information ...

If other, logic components are valid, such as a quad NAND gate or hex inverter, this gets much easier. A portion of CD4093, or xx74xxx14 in any flavor, plus 1 diode, is a classic approach. You don't say what the time interval T is, but your schematic suggests a little under 0.33 s. Any hysteretic gate can handle the relatively slow risetime.

Personally, I would go with Spehro's schematic, but:

  1. Use a 2nd transistor instead of OA2.

  2. Add one resistor for hysteresis.

  3. Change both transistors to 2N7000 MOSFETs. This allows a much higher impedance timing network, which shrinks the size of the timing capacitor.

  4. Eliminate the input differentiator network. My read of your first post is that it is not needed because the input triggering pulse always is shorter than the monostable period. If that is not the case (if the input signal might stay high longer than T), then keep it in.

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Thanks to Michal Podmanický's answer I came up with the system I wanted. I replaced the RS latch with a non-symmetrical Schmitt trigger made of one opamp, with its thresholds set at one third and two thirds of 3.3 V. This means the high duration is : formula, which is 330 ms with the values of the schematic.

Schematic

This gives the exact results I wanted in simulation (upper half is input, lower half is output) :

enter image description here enter image description here

And when tried in practice, it also worked as expected :

enter image description here enter image description here

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