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I do not have a clear idea of what load capacitance is. I am looking forward to use the ADF4106 PLL with a ~580 MHz VCO to synthesize the frequency.

For the reference input to the PLL, I wanted to simply use a CMOS active crystal oscillator, directly connect it to the REFin pin, with only the AC coupling capacitor (that blocks DC).

But now I noticed this term in the datasheet: "load capacitance". The oscillator I want to use is an SG7050CAN ~3 V CMOS active crystal oscillator which I will use at 24 MHz. The datasheet says: Load capacitance, L_CMOS: 15 pF max.

I want to understand, in a simple, application oriented manner, what this load capacitance is. I mean, how do I control this load capacitance? What do I need to do?

Can I just connect it directly to the REFin pin of the ADF4106 PLL with just the DC decoupling capacitor in between? The ADF4106 datasheet says that the input capacitance of its REFin pin is max. 10 pF.

Does this mean I can simply connect the SG7050CAN output to the REFin pin, keeping the trace as short as possible on the basic FR4 PCB that I will use?

NB: I am quite loaded with the project overall, so I am keen to just understand the connection and load capacitance controlling rule(s) to get the oscillator connected to the PLL reference input as simply as possible, and less interested in detailed theory or anything like that.

And in the website of Epson, manufacturer of the SG7050CAN oscillators, I read that they incorporate loading capacitance or supporting circuitry like that internally in their oscillators. Thus, their oscillators can be used to run ICs directly, forming standardized components and simplifying the design process.

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  • \$\begingroup\$ 15pF - 10pF leaves 5pF for parasitic (PCB track) capacitance. Keep the track short and don't run ground plane under it. \$\endgroup\$ Nov 29 '21 at 22:03
  • \$\begingroup\$ Thanks bro, good suggestion and reminder. I was thinking about this trace to ground plane capacitance thing. And seems like the 15 pF limit would not be quite a problem hopefully, keeping the trace just a little bit short should restrict the stray capacitance (or trace capacitance) within 5 pF. \$\endgroup\$
    – shafik
    Nov 30 '21 at 0:46
  • \$\begingroup\$ However, I have learnt that the trace capacitance on a basic FR4 would not usually exceed 1 pF/cm. So, if we keep the oscillator out pin within 3 cm (3 pF trace capacitance between the out pin and the PLL REFin pin), we should be able to safely keep the ground plane and not clear it. \$\endgroup\$
    – shafik
    Nov 30 '21 at 2:36
  • \$\begingroup\$ If you can get it closer than 3cm, so much for the better, but there's probably no point worrying about the difference between 1 and 1.5cm. \$\endgroup\$ Nov 30 '21 at 13:55
  • \$\begingroup\$ Yeah. I understand. \$\endgroup\$
    – shafik
    Nov 30 '21 at 14:54
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Clock trace length is not critical for pF, but is important for EMI reasons. Let me give you the long explanation 1st and conclusion last.

The CMOS driver is generally balanced equally impedance driver to give equal load current for each state and equal rise/fall time. Yet from process limitations and differences in Pch. Nch will have differential offsets in Ron and Miller Capacitance at each state 0,1. This results in a spec for symmetry of the square wave for each version that also affects operating current and drive current variations.

Thus the standard way to define these variations is to use a fixed load C in the parameter tolerances. Smaller load C reduces risetime, but is not necessarily a max load or an optimal load. Smaller load C is necessary only for max f which is rated with "no load". Understand that slew rate currents come from the nearby decoupling cap are affected by load C which suppress the voltage ripple from affecting nearby circuits and radiated EMI in the loop area.

Since \$dVc/dt = Ic/C \$ and CMOS \$Z_{ol}=V_{ol}/I_{ol}\$ for the Nch and likewise for the Pch \$Z_{oh}=(V_{DD}-V_{oh})/I_{oh}\$. These Z values = the RdsOn values are also Vdd/Vgs dependent which are often consistent within each family of devices rated at the same Vdd max lile 5.5V or 3.6V etc. but have wide process tolerances (25% to 50%)

If the load Cin = 10 pF and asymmetry test std was 15 pF then how much trace length and thus capacitance can you work with to minimize? ( is the next question)

Background on stripline or PCB interconnects in general

Trace impedance over a ground plane is lower than without and thus higher capacitance ~ tp 0.5 pF /cm. This reduces emissions but unless it is a a high layer count with very thin FR4 gap or might be at least 120 Ohms, if track w/h = 2 then you are close to 50 Ohms which for a short track, reflections are not a problem, so neither is Zo, but radiated noise might be. So a ground plane is needed for control of emissions to reduce the current loop area. RdsOn near 25 ohms for 3.6V logic and 50 ohms for 5.5V logic. Capacitance is linear with track width when the gap to gnd plane is much smaller than width but when w/h ratio of track geometry is << 1 the pF /cm does not change much. Recall 1st, 2nd & 3rd order effects of a plane, line and point charge vs E-field

So for 4 layer boards consider for a trace width,w and 2nd layer gnd cap, h for w/h = 0.2mm/0.9mm the trace capacitance is 0.5 pF/ cm. Thus a direct connection with 5 pF trace capacitance is 10 cm!

For 2 layer board it is 0.42 pF/cm. and 0.2mm is almost an 8 mil wide trace.

Conclusion

Thus the load=15 pF is what you might encounter with different chip loads and is not a "Target load" but perhaps a practical limit at max f. It only affects duty cycle slightly and also limits risetime for the RC time constant. If you are using both edges for certain functions, that may affect timing margins at the max f, otherwise it is not a worry with ~ 0.5 pF/cm on a trace.

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  • \$\begingroup\$ Okay. Thank you, very educative. So, even with the ground plane below, the capacitance is ~0.5 pF (I did not calculate myself and it would be a lengthy process for me) as you have stated. This should mean I can simply just place the oscillator anywhere around the REFin pin of the PLL, unless it is very very far away. Who would put the oscillator 10 cm away anyway. \$\endgroup\$
    – shafik
    Nov 30 '21 at 1:01
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It means that the oscillator has a CMOS output which is within the datasheet specs if the capacitive load that it needs to drive is below the maximum listed in the datasheet.

As CMOS inputs are mainly capacitive, the loading is due to the PLL input pin capacitance and of course the PCB wiring also are just conductors with insulation in between so capacitance comes from PCB wiring too.

Basically longer wiring has longer capacitance so figure out if the 15 pF drive capability is enough to drive 10 pF load with stray wiring capacitance. You may also need to take source and/or sink termination into account. If the load is more than drive ability, you need a buffer.

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  • \$\begingroup\$ Thanks. From what I have understood, keeping the oscillator out pin just adjacent to the REFin pin of the PLL should keep the trace capacitance within 5 pF, keeping the total capacitance within 15 pF. \$\endgroup\$
    – shafik
    Nov 30 '21 at 0:50
  • \$\begingroup\$ re:" if the 15 pF drive capability " If you operate at only 24 MHz you can certainly drive more than 15 pF. So it is incorrect to interpret that as the drive capability (-1 ;) that is just a datasheet reference load for max f at Vmin. for relative calculations of voltage margins on output signal. \$\endgroup\$ Nov 30 '21 at 4:25
  • \$\begingroup\$ @TonyStewartEE75 For the CAN part it does say that output load condition is 15 pF max and for CCN part it is 50pF. It says elsewhere that parameters are measured at 15 pF load. It would imply that there really is a 15 pF limit for the CAN part the OP is using. I agree "drive ability" may have been a wrong term here, but I still interpret 15pF as the maximum capacitive load for CAN part and 50 pF for CCN part. \$\endgroup\$
    – Justme
    Nov 30 '21 at 5:25
  • \$\begingroup\$ You may, (consider it maximum) but knowing that it is a reactive load it only applies to max f at conditions given for CMOS logic outputs. And thus could be increased slightly at lower f's if one had to, for reasons I answered. ( as well as RC*f would be constant) \$\endgroup\$ Nov 30 '21 at 7:29

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