I do not have a clear idea of what load capacitance is. I am looking forward to use the ADF4106 PLL with a ~580 MHz VCO to synthesize the frequency.
For the reference input to the PLL, I wanted to simply use a CMOS active crystal oscillator, directly connect it to the REFin pin, with only the AC coupling capacitor (that blocks DC).
But now I noticed this term in the datasheet: "load capacitance". The oscillator I want to use is an SG7050CAN ~3 V CMOS active crystal oscillator which I will use at 24 MHz. The datasheet says: Load capacitance, L_CMOS: 15 pF max.
I want to understand, in a simple, application oriented manner, what this load capacitance is. I mean, how do I control this load capacitance? What do I need to do?
Can I just connect it directly to the REFin pin of the ADF4106 PLL with just the DC decoupling capacitor in between? The ADF4106 datasheet says that the input capacitance of its REFin pin is max. 10 pF.
Does this mean I can simply connect the SG7050CAN output to the REFin pin, keeping the trace as short as possible on the basic FR4 PCB that I will use?
NB: I am quite loaded with the project overall, so I am keen to just understand the connection and load capacitance controlling rule(s) to get the oscillator connected to the PLL reference input as simply as possible, and less interested in detailed theory or anything like that.
And in the website of Epson, manufacturer of the SG7050CAN oscillators, I read that they incorporate loading capacitance or supporting circuitry like that internally in their oscillators. Thus, their oscillators can be used to run ICs directly, forming standardized components and simplifying the design process.