A SDRAM module is divided into chips. And those chips into banks. Banks can have different row and column lengths.

When reading a given address, I feed the address to the memory specifying the address I want to read (at a 64 bytes granularity). Then, depending on the encoding of the address, one or more banks will be read from one or more chips.

The points I cannot figure out are:

  • How does a single read (from the memory perspective) generate 64 bits? How is the internal logic built? Is every bank able to feed 64 bits at once?
  • What is the trade-off between having more chips or having more banks? Is it just a matter of bandwidth?
  • 4
    \$\begingroup\$ First misconception, banks are not the number of bits you can read in parallel. \$\endgroup\$
    – Justme
    Nov 30, 2021 at 12:30
  • 4
    \$\begingroup\$ You need to read and understand the datasheet for the sdrams you are using. Thinking about multiple chips, modules and cache lines is noise at this point. The basics are the chip is arranged as rows and columns. You latch the row and column addresses then you can read a number of bits in succession. The datasheet will outline the sequence and timing. Once you’ve got the basics, everything else should fall into place. \$\endgroup\$
    – Kartman
    Nov 30, 2021 at 12:35
  • \$\begingroup\$ Hmm I think your understanding of Banks is wrong.... I found this video series useful: youtu.be/Mhqi70OPW0o \$\endgroup\$
    – Mitu Raj
    Nov 30, 2021 at 12:37
  • 1
    \$\begingroup\$ A warm welcome to the site. Please note it's a Q&A site, not a discussion forum and can't be a personal tutorial service. The internet has mountains already written on this subject and you'll find answers there easily enough. Here, people will help you take the next step - if your questions show you've done as much as you possibly could. Which this doesn't, I'm afraid. Please edit your question and greatly improve it. Show your own work and your own findings in considerable detail. The better the quality of your questions, the better the quality of the answers you will attract. Again, welcome. \$\endgroup\$
    – TonyM
    Nov 30, 2021 at 12:47
  • \$\begingroup\$ @TonyM thank you. I did some research but I couldn't figure out the questions I'm asking. I edited my post to clarify the points that are not clear to me. \$\endgroup\$
    – Franks
    Nov 30, 2021 at 13:30

1 Answer 1


A single read actually reads an entire row (usually something like 2 or 4kbits) at once, selected by the Row Access Strobe (RAS), addressed to one bank. But you're not done yet, all this data is still within the DRAM chip.

What data you select from this row depends on how you use the Column Access Strobe(CAS), the DRAM generation, and how you initialised it. To get 64 bits on a x8 wide device, you'd use a burst length of 8, on most modern (DDR-n) SDRAMs, which are aimed at systems with cache memories, so that the burst length is aligned with the L1 cache line size.

Access patterns supplying all 2kbits require Page Mode, where repeated CAS strobes keep supplying successive data until either a Burst Terminate or Precharge command. Page Mode, unfortunately, hasn't been seen in years (outside of special graphics memory devices which may or may not still exist).

I think the last DRAM generation to support Page Mode was (SDR) SDRAM circa 2000, and it was dropped with the first (or maybe second) DDR generation. Which is a pity, because Page Mode was great for streaming vast amounts of data through a custom processor on an FPGA. (You can mimic Page Mode via a carefully timed sequence of short bursts, but it's much less convenient)

Banks come in by allowing multiple Row accesses (max. one per bank) to be in progress at once. Having accessed a row in one bank, you can leave it open (for a while, like 8 ms or one refresh period) while also accessing a row in another bank. Which is great for allowing things like copying data from one array to another (perhaps via some intermediate processing stage) by reading from one (or more) banks and writing to another.

  • \$\begingroup\$ Adding more banks to a chip only provides more bandwidth? Or is also for timing reasons for control signals? \$\endgroup\$
    – Franks
    Nov 30, 2021 at 16:06
  • \$\begingroup\$ It doesn't add more bandwidth but it can reduce latency for specific access patterns. \$\endgroup\$
    – user16324
    Nov 30, 2021 at 17:25

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