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I am designing an inverting voltage regulator using a LT3758 controller to generate -15 V from a 12 V / 5 V input. This is a non-isolated regulator.

My biggest concern implementing the design is if the regulator is going to inject any noise into GND because that can cause many other issues on the board.

I had a thought of providing a pi filter or LC filter using a ferrite bead between my board's GND and the regulator's GND (just like how we provide a filter to Vin in a positive voltage regulator). But in TI's document SNVA559 it is shown that inductance between GNDs can cause ground bounces, which is what I want to avoid.

What is a proper solution to avoid switching noise in the negative voltage regulator?

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    \$\begingroup\$ Any regulator will inject noise, negative or positive does not really matter. The primary factor to limit noise in switching systems is the PCB layout. \$\endgroup\$
    – Damien
    Dec 2, 2021 at 6:26

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One does not simply 👌 "inject noise into ground", because there is no "ground" 🥄.

There is a ground plane (hopefully) and it has an impedance, therefore if current flows through it, a voltage drop will appear between different points on the ground plane. This common impedance coupling means every chip or other device that has a "GND" pin will get a different 0V reference from the others, and then noise is introduced into your signal.

enter image description here

Your converter has two current loops:

  • the hot loop (in red), with HF square wave currents ;

  • the warm loop (blue), with sawtooth currents.

The most noxious is the hot one, because square waves have much more HF harmonics than sawtooth.

The most important things are:

  • Make sure the currents from both loops do not flow in your ground plane, by connecting the GND pins of input cap, output cap, Rsense, and L1B together on the same spot, or on a small copper island on toplayer which is then connected to the ground plane with a cluster of vias. You can also put it in a corner and not in the middle of the board, and if you don't like common mode noise, don't put it between two connectors, but on the side.

  • Minimize the area of the hot loop first, then the warm loop second, which will reduce EM field emissions in proportion. For the hot loop, you can put D1 and Cout very close to M1. For the warm loop, forget about "laying it out like the schematic" with the input on one side and the output on the other side. If you put the input and output on the same side, with the GND pins of Cin and Cout next to each other, it will be much easier.

  • A separate via to ground plane for the feedback's ground reference, so it is not contaminated by switching noise.

The datasheet layout doesn't fulfill all these conditions, but the placement of the ground vias is excellent. Note the GND reference of the chip is its own GND pin, and it will regulate in reference to this, so it's good to place the ground vias under the chip too. Also the feedback sense point is taken after Cout, which is important since it avoids spikes on your feedback voltage.

Further reading.

enter image description here

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