Not unless there is an excessive delay between the clock reaching a Shift Register (SR) D-type Flip-Flop (DFF) and the clock reaching the DFF following it.
Each DFF doesn't update its Q outputs with its D input level instantly. There is a delay as it travels through the DFF's internal circuitry. So each DFF has not produced a new Q output while it is latching in the Q of the previous DFF, which also has not produced a new output.
A perfect clock arrangement would have the clock reaching the clock input of all DFFs simultaneously. On the clock's active edge, the DFFs would latch in their D input levels and, after a delay, update their Q outputs.
In reality, there will be a skew between the clock signals at the inputs of all DFFs in the SR. A correctly connected-up SR ensures that this clock skew is less than the DFF D->Q 'travel time'.
The skew can be negative, so that the clock reaches the final DFF in the SR first, then reaches the DFF slightly before and so on. But this impacts the timing of any clocked logic driving the first DFF in the SR, so that has further timing consequences for the overall circuit.
For a PLD (FPGA/CPLD) or ASIC, the fitter software will take care of that while it tries to meet any minimum clock requirement that's been specified.