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enter image description here

The graph above shows the output of a shift register.

The output of Qa is sampled at the first rising edge on data input. the voltage is building up during that time. Will it cause metastability since the output of Qb is also sampled at the first rising edge on Qa? The output of Qb is zero at the first rising edge, does it mean that the data sampled at that time is zero?

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  • \$\begingroup\$ Would need to know the specified setup and hold times for the input; as drawn the graph suggests that the setup time (before rising edge of Clk) is expected to be zero. Some older devices (truly ancient stuff) require input to be stable some time before the clock edge. \$\endgroup\$
    – MarkU
    Dec 2 '21 at 8:48
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    \$\begingroup\$ Does this answer your question? Wrong data clocked in when using direct daisy chains of 594/595 shift-registers \$\endgroup\$
    – tobalt
    Dec 2 '21 at 10:18
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    \$\begingroup\$ The diagram OP showed implies a single part - a 4-bit shift register of TTL, LSTTL, or CMOS vintage. In discrete components like these, the IC vendor ensures that the setup and hold times of the individual flip flops internal to the device are met, by design. \$\endgroup\$
    – SteveSh
    Dec 2 '21 at 13:22
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    \$\begingroup\$ @devnull - You're right in that most manufacturers do not specify min prop times, which would be needed to guarantee meeting setup and hold times. Back in the days of designing with discrete devices, many engineers (myself included) would take the typical prop time number and derate it by some factor, 2X, 3X, 5X, to come with a reasonable SWAG for minimum clock to output delays. \$\endgroup\$
    – SteveSh
    Dec 2 '21 at 14:42
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    \$\begingroup\$ There's nothing in OP's post, title, or tag that says VHDL, Verilog, or FPGA. And besides the timing diagram he showed with labels QA, QB, QC, and QD for the outputs are labels that are typically used with discrete digital devices. Look up 54LS161 for a typical example of this nomenclature. \$\endgroup\$
    – SteveSh
    Dec 2 '21 at 15:21
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Data sheets rarely put a warranted time for which the output will remain stable after the clock pulse. It's therefore difficult to prove from data sheet timings alone on individual pins that shift register timings can be met.

However, the ability to build shift registers out of flip-flops is such a common requirement, that in practice, all flip-flop families are designed so that when an output drives an input of the same family, the setup and hold times will be met by the output delay times. A flip-flop family that did not meet this requirement would be unusable, and rapidly shunned by all users.

Within an FPGA, the issue becomes even more moot, as the layout/timing tools have to take account of every bit of variable delay through signal switching devices, and so do the whole job for you (if you've set the constraints up correctly).

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Not unless there is an excessive delay between the clock reaching a Shift Register (SR) D-type Flip-Flop (DFF) and the clock reaching the DFF following it.

Each DFF doesn't update its Q outputs with its D input level instantly. There is a delay as it travels through the DFF's internal circuitry. So each DFF has not produced a new Q output while it is latching in the Q of the previous DFF, which also has not produced a new output.

enter image description here

A perfect clock arrangement would have the clock reaching the clock input of all DFFs simultaneously. On the clock's active edge, the DFFs would latch in their D input levels and, after a delay, update their Q outputs.

In reality, there will be a skew between the clock signals at the inputs of all DFFs in the SR. A correctly connected-up SR ensures that this clock skew is less than the DFF D->Q 'travel time'.

The skew can be negative, so that the clock reaches the final DFF in the SR first, then reaches the DFF slightly before and so on. But this impacts the timing of any clocked logic driving the first DFF in the SR, so that has further timing consequences for the overall circuit.

For a PLD (FPGA/CPLD) or ASIC, the fitter software will take care of that while it tries to meet any minimum clock requirement that's been specified.

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  • \$\begingroup\$ Could you please inform, for a discrete DFF IC, which parameter indicates this minimal "D->Q 'travel time'". Propagation delay frequently comes with just a typical value, not limits. \$\endgroup\$
    – devnull
    Dec 2 '21 at 9:25
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    \$\begingroup\$ @devnull, I considered that but deliberately left it out. OP's question is tagged for VHDL/Verilog so they're looking at FPGAs, not 7474s. Values change between FPGAs. \$\endgroup\$
    – TonyM
    Dec 2 '21 at 9:36
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    \$\begingroup\$ @devnull - Many discrete digital IC's specify a max propagation (travel time) time, for a given temperature range and VCC range. If you're using a part that doesn't, and you care about that parameter, you need to find a different part to use. \$\endgroup\$
    – SteveSh
    Dec 2 '21 at 13:13
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Since this question is tagged with [vhdl] and [verilog], I will answer the question from an ASIC/FPGA design perspective.

The problem you describe is entirely possible. If the clock arrives at the second stage significantly later than the first stage, the second stage may enter a metastable state since its input has already started to change. However, this is precisely what timing analysis is meant to prevent. Modern synthesis tools are timing driven and will ensure that cells and routing is laid out such that no metastability issues can occur. If the tool is unable to do this for some reason, the final timing analysis will mark the path as a timing violation.

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