# How to design an EMI Filter for AC/DC PSU

I am designing a single phase MIL-STD-461 AC/DC PSU. I have the following requirements to the PSU:

1. It needs to operate with an input voltage from 100Vrms up to 310Vrms.
2. Operating frequency 45-65 Hz
3. Current rating of at least 3 Arms (important for choosing inductors and CM choke)
4. Compliant to MIL-STD-461G conducted emissions

I have chosen a PFC AC/DC module that works as intended. However, the accompanying filter is only rated up to 264Vrms (the PFC AC/DC module has sufficient rating). The filter rating is mainly due to the use of X2 X7R safety capacitors in the filter. The fundamental circuit diagram of the filter is shown in this schematic from the filter datasheet (component values not specified and damping resistors not included).

The CM and DM attenuation performance of the filter with 50 Ohm source and load impedance is shown in this plot:

It seems that most commercial and military filters are rated up to 250-264Vrms, and commercial filters also have unspecified attenuation for frequencies under 150 kHz. This is why I am looking into designing my own filter, where I plan to use class 1 safety rated capacitors in order to increase the voltage rating. I think that I have two options for specifying the needed attenuation of the filter.

1. Measure the spectrum of the PSU without any filter and see at which frequencies and how much I am over the limit.
2. Specifying the same attenuation as in the plot shown above (given that the manufacturer of the PSU has tested the PSU/filter combination against the standard).

I would prefer option 1, but unfortunately I am unable to measure the spectrum of the PSU at this point in time, because our LISN filters and analyzer is out for calibration.

Even if I was able to measure the spectrum of the PSU, the question remains the same: "How do I design an EMI filter that meets a specified attention performance"?

I am not aware of an analytical approach to multi-stage filter design, and from the differential-mode attenuation plot, I can identify three different cut-off frequencies.

I would think that the design of EMI filters to meet a specified attentuation would be something that was "standardized" to some degree, given that almost all electronic products require a filter, but during my research I haven't been able to find this approach.

So, to summarize, these are my main questions:

• Given the required attenuation for a given frequency band, how should I design the EMI filter?
• How to choose topology?
• How to choose component values?
• Are there any SW packages available for filter synthesis and/or simulation to aid the design? (I am comfortable with spice simulation, but without a methodical way to choose topology and component values this becomes hit and miss).

• Given the required attenuation for a given frequency band, how should I design the EMI filter?

You design the filter based on the required attenuation needed for the frequency bands in question. You appear to be asking for a general solution but, I'm saying that for a particular requirement, you design the filter to suit that requirement. I'm sorry that you might think this isn't helpful but, sat where I am, that's how I do it. To try and gives rules and options for an unspecified requirement is unreasonable and impractical.

For the specific filter design shown in your question, here's what it does generally: -

Breakdown each one in turn if you want to learn about them - using a simulation package to mimic the behaviour is something I highly recommend. Without a good data sheet for that filter, I wouldn't begin this process. Collect the information, understand it then simulate.

• How to choose topology?

You study the requirements for the filter and figure out what topology is likely to be most successful. This may mean a fairly standard filter as per the one shown in your question or, it might mean doubling up on those filters to cover overlapping bands to obtain maximum spectrum-wide performance. Note here that I'm suggesting that a single simple EMI filter can easily run-out-of-steam in the higher spectrum but be perfectly good in the lower part of the spectrum. Sometimes, it's necessary to put different inductors in series so that one inductor (that is good for the lower spectrum) is supplemented by another series inductor that is good for the higher part of the spectrum. I'm talking about problems of self-resonant frequency and how this factor can morph an inductor into a capacitor and therefore let higher frequency interference through at ease.

• How to choose component values?

I use a simulation package (as do most pros) and that means starting off from a blank sheet and developing ideas that eventually yield component values. It's a suck-it-and-see approach. Sure, the experienced guy will have something in mind as a starting point so, as you gain experience, this process becomes easier but, for the 1st time designer, it's a daunting process that rapidly gets easier as you start to believe in yourself.

• Are there any SW packages available for filter synthesis and/or simulation to aid the design?

Absolutely yes. I use micro-cap 12 - that's a download link. Many people use LTSpice and there are others but, I'm an experienced micro-cap user and wouldn't bother with other sims. But, the biggest mistake is not understanding the real characteristics of inductors IMHO. Make you models with great care and you'll get good results. Also, you might be surprised to find how relatively easily you can model the differential current waveforms that you design produces. You don't need a great degree of precision here; if your current waveform is roughly mimicked to within 10% of actual that will be good enough for use in a simulator. You must also model your LISNs too - that's really easy so don't skimp on the simulation is my advice.

• I am comfortable with spice simulation, but without a methodical way to choose topology and component values this becomes hit and miss

Yeah, for sure it's hit and miss but, so is any design process and I'm not just talking EE designs. That's what design is all about. That's what makes design so interesting (and frustrating). Get used to it. I mentioned the "suck-it-and-see approach" approach earlier.

I am not aware of an analytical approach to multi-stage filter design

There are many, many analytical approaches; you just haven't found them or not recognized them yet. The main one that springs to mind is cascading pi filters to get massive differential-mode attenuation above certain frequencies but, as with any theoretical approach, the devil isn't in the theory but in component selection and understanding component limitations.

my intention was to ask how I could go about mimicking the attenuation as plotted in the graph, using the circuit topology as shown

The data sheet says this: -

• Total Common-Mode Capacitance 2 x 9.4 nF
• Total Differential-Mode Capacitance 336 nF

This tells me that you can assume this: -

• C3 = C4 = 4.7 nF
• C1 + C2 = 332 nF (336 nF minus C3 in series with C4)

The data sheet also says this: -

• Tcase = 25ºC 230 mΩ (series resistance of filter)
• Zero Load, 115 Vrms 60 Hz 0.1 W
• Zero Load, 115 Vrms 400 Hz 0.6 W

Hence, you can start to figure out the values of series resistance especially in those inductors that I've marked L1 above. From the attenuation graph you can see that at about 1 kHz the DM attenuation is about 7 dB so you can double check the numbers and, because this is such a low frequency you can assume that the inductors are not playing a significant role in opposing currents.

The front page of the data sheet says this: -

• Differential & Common-mode Output Attenuation >40dB @ 250kHz

But, if you are choosing values, it should be more like 40 dB attenuation at 120 kHz: -

Then, just keep plugging away at it covering every little hint in the data sheet you can find. Cross-check the numbers and you're good to go. It'd probably take me 4 hours but, it might take you 2 days. That's the way it is unfortunately; experience trumps inexperience!

• Thank you for your input @Andy aka. I agree that it is important to understand the fundamentals first. A few follow up questions: Your green marking also includes the two in-line inductors for CM attenuation. I am of the understanding that series inductors provide DM attenuation, unless coupled as a CM choke. Is this incorrect? With respect to this specific questions, my intention was to ask how I could go about mimicking the attenuation as plotted in the graph, using the circuit topology as shown. Specifically how to find the component values. Sorry if that wasn't clear. Dec 2, 2021 at 12:56
• (1) If the two inductors inside the green box are pretty much the same value then they will act as a decent CM filter in conjunction with the two capacitors (also inside the green box) that are connected to earth. A regular two coil CM choke will have roughly the same CM characteristic as the individual inductors but, will be let differential signals through fairly unimpeded (both a good thing and a bad thing depending on how you look at it and what you are aiming for).... Dec 2, 2021 at 13:08
• (1 continued) The individual inductors therefore also act as a DM filter and, in your application, it's likely that where it's positioned, that is indeed the best place for this to be because it'll trap differential noise produced by your PFC circuit from getting up-stream to the incoming power supply. (2) To answer what appears to be your 2nd question in the comment above, you need to provide data sheet links to that component at the very least @Lunde Dec 2, 2021 at 13:11
• (1), thank you for the clarification. (2), the link to the data sheet. Dec 2, 2021 at 13:55
• @Lunde what about the link to the PFC device that recommends the use of that filter. Dec 2, 2021 at 14:08

Normally, your question is a topic of an EMC book. I'll try to keep as short and organized as possible. Remember that the initial design can be done on paper, but finalizing it still requires measurement.

First of all, I've never worked on MIL-spec and related standards. I'm working on consumer and automotive, so, just as an example, I'll try my best to explain an initial design from scratch for that areas. The limits may not suit your needs, so you may need to make necessary modifications.

Image Source

The first thing you need to know is the switching frequency of the load/converter. Yours is a PFC pre-regulator so its switching frequency might not be constant (i.e. modulated with input sine). If it's operating in BCM (Boundary/Critical Conduction Mode a.k.a. CrCM) this gets worse because the switching frequency is in quite a wide range (e.g. 35kHz to 250kHz). Knowing this is important because it'll be used in harmonic-based design analysis.

Here's an example for a converter operating at 50kHz.

1- Noise Levels

Since the converter is operating at 50kHz, there'll be a noise peak at 50kHz with harmonics at 3f, 5f, 7f etc i.e. odd harmonics. Industrial EMC standards do not care the noise levels at frequencies below 150kHz. So my interest is the 5th harmonic i.e. 250kHz and above. If the input diode bridge has 1.5V drop then the fundamental amplitude will be

$$\mathrm{A_0=20\log\frac{1.5V}{1\mu V}=123.5 \ dB\mu V}$$

and the 5th harmonic's amplitude will be (n=5)

$$\mathrm{A_5=20\log\frac{4\cdot 1.5V}{n\ \pi \ 1\mu V}=111.6 \ dB\mu V}$$

2- Attenuation

The quasi-peak limit for industrial applications is 65 dBμV. Putting a 4 dBμV safety margin yields an attenuation of $$\mathrm{D= A_5-65-4=51dB\mu V}$$

3- Corner Frequency

I want my filter to attenuate the frequencies 250kHz and above with a slope of S = +40dB per decade. So,

$$\mathrm{-D = S\log \frac{f_c}{f_5} = -51=+40\log \frac{f_c}{250 \ kHz} \\ \Rightarrow f_c=250k \ 10^{(-51/40)}=13.3kHz}$$

4- Component Selection

This part is a bit tricky. You can't randomly select CX because it'll affect the power factor. You can't randomly select L because you need to take the input current into account, and L's stray inductance is useful.

Assuming the input current at low line (i.e. 100Vrms) is 2A. So the current rating for L should be at least 2A.

Remember that L and CY capacitors are for common mode noise filtering. And the stray/leakage inductance of L along with CX provide filtering for differential mode noise.

Let's start with a 3mH / 3A common mode choke. Assuming it has a stray inductance of 1% i.e. 30μH. So,

$$\mathrm{f_c= \frac{1}{\sqrt2 \cdot 2\pi\sqrt{L_s\cdot C_X}}} \\ \Rightarrow \mathrm{13.3k = \frac{1}{\sqrt2 \cdot 2\pi\sqrt{30\mu\cdot C_X}} \Rightarrow C_X = 2.4 \mu F}$$

and

$$\mathrm{f_c= \frac{1}{\sqrt2 \cdot 2\pi\sqrt{L\cdot C_Y}}} \\ \Rightarrow \mathrm{13.3k = \frac{1}{\sqrt2 \cdot 2\pi\sqrt{3m\cdot C_Y}} \Rightarrow C_Y = 23.9 nF}$$

So the initial design is done. The next step is to choose the nearest standard values and run simulations then build and measure afterwards.

FINAL NOTES

This is an iterative approach and may not give the desired results right in the first time. For example, a CX of 2.4μF might be too high and thus decrease the PF too much (i.e. under 0.9) so you may need to decrease CX to, say, 1μF. Then to achieve the same differential mode filtering performance, you might need series inductances like shown in the schematic in your question, because the stray inductance of L will not be sufficient.

So, after a few iterations and measurements, you'll get the best results but the example I tried to give above might be a good start.

• Thank you for your input @Rohat. I will try to give it a go and see how if I am successful. Dec 2, 2021 at 13:00