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Suppose that the circuit has several inputs from an external circuit which do not have an effect until the clock next rise edge due to using synchronous flip-flops. If the external circuit sends several inputs and because there is a different propagation delay for each line one or two inputs arrive late after the clock has rise and after other inputs were activated will the circuit encounter a hazard?

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    \$\begingroup\$ Of course it will be a hazard. The calculation at that cycle will have wrong inputs and will probably produce wrong outputs. \$\endgroup\$
    – Eugene Sh.
    Dec 2, 2021 at 15:08
  • \$\begingroup\$ Do you have any example circuit to demonstrate your question? \$\endgroup\$
    – Mitu Raj
    Dec 2, 2021 at 15:10
  • \$\begingroup\$ @EugeneSh. but then how synchronous guarantees no race \$\endgroup\$
    – dev65
    Dec 2, 2021 at 15:10
  • \$\begingroup\$ @MituRaj no I just though of this situation \$\endgroup\$
    – dev65
    Dec 2, 2021 at 15:11
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    \$\begingroup\$ Of course we are talking about the same thing. "how to ensure this does not happen " - by calculating the critical path delay and setting the minimal clock cycle accordingly. \$\endgroup\$
    – Eugene Sh.
    Dec 2, 2021 at 15:20

2 Answers 2

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If the delays are constant and those inputs always arrive after the clock edge, there is no race condition, there is a pipeline error.

You can solve this by (for example) delaying the faster input by a clock period to match the other inputs : this Q&A illustrates a pipeline error and its resolution.

If the delays are variable (or the input is completely unsynchronised) there is a race condition, and several bad things can happen when the input arrives at approximately the same time as the clock edge.

Very rarely, this results in metastability, where the two (data and clock) arrive at precisely the same instant so that the changing data cannot be resolved as either '0' or '1'. This can result in an intermediate output state which takes a long time (worst case, more than a clock period) to resolve into a valid logic level. (In modern FPGA technology, "very rarely" translates into "maybe once or twice before the heat death of the universe" though in the early 2000s it was a more significant problem.

Much more commonly, (and often confused with metastability) the input signal arrives at two or more destinations within the circuit, before the clock edge at one register, and after it at another, and is thus seen as both '0' and '1' by different parts of the circuit.

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  • \$\begingroup\$ I understand this but how to make sure the inputs will not arrive around the edge if the two circuits have different clock rates ? \$\endgroup\$
    – dev65
    Dec 2, 2021 at 16:20
  • \$\begingroup\$ @dev65 that is not what your post asks ... please post a new question, so that it is not burried inside a comment \$\endgroup\$
    – jsotola
    Dec 2, 2021 at 16:34
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    \$\begingroup\$ that should be a new question ... this site is not a forum \$\endgroup\$
    – jsotola
    Dec 2, 2021 at 16:36
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    \$\begingroup\$ If you have two signal sources that are not synchronous, then you have to synchronize them. There is no way around it. Different clocks (unless it is just a phase) imply that you will get more different signals from one source than from the other in a unit of time, and it does not make any sense if you want to process all of them. \$\endgroup\$
    – Eugene Sh.
    Dec 2, 2021 at 16:41
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    \$\begingroup\$ "Input synchronizer" as a search term should yield myriad examples. \$\endgroup\$
    – user16324
    Dec 2, 2021 at 18:25
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I found this problem in Wikipedia and it seems to be called Metastability problem. According to wikipedia this problem can't be solved entirely and there is no metastable-proof flip-flop. For circuits that is entirely made by the designer the designer must make sure they are metastable and for circuits that is external is to connect two or more flip-flops in a chain.

from wikipedia:

Timing parameters

Flip-flop setup, hold and clock-to-output timing parameters The input must be held steady in a period around the rising edge of the clock known as the aperture. Imagine taking a picture of a frog on a lily-pad.[29] Suppose the frog then jumps into the water. If you take a picture of the frog as it jumps into the water, you will get a blurry picture of the frog jumping into the water—it's not clear which state the frog was in. But if you take a picture while the frog sits steadily on the pad (or is steadily in the water), you will get a clear picture. In the same way, the input to a flip-flop must be held steady during the aperture of the flip-flop.

Setup time is the minimum amount of time the data input should be held steady before the clock event, so that the data is reliably sampled by the clock.

Hold time is the minimum amount of time the data input should be held steady after the clock event, so that the data is reliably sampled by the clock.

Aperture is the sum of setup and hold time. The data input should be held steady throughout this time period.[29]

Recovery time is the minimum amount of time the asynchronous set or reset input should be inactive before the clock event, so that the data is reliably sampled by the clock. The recovery time for the asynchronous set or reset input is thereby similar to the setup time for the data input.

Removal time is the minimum amount of time the asynchronous set or reset input should be inactive after the clock event, so that the data is reliably sampled by the clock. The removal time for the asynchronous set or reset input is thereby similar to the hold time for the data input.

Short impulses applied to asynchronous inputs (set, reset) should not be applied completely within the recovery-removal period, or else it becomes entirely indeterminable whether the flip-flop will transition to the appropriate state. In another case, where an asynchronous signal simply makes one transition that happens to fall between the recovery/removal time, eventually the flip-flop will transition to the appropriate state, but a very short glitch may or may not appear on the output, dependent on the synchronous input signal. This second situation may or may not have significance to a circuit design.

Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may be characterized with either Setup/Hold or Recovery/Removal times, and synchronicity is very dependent on the design of the flip-flop.

Differentiation between Setup/Hold and Recovery/Removal times is often necessary when verifying the timing of larger circuits because asynchronous signals may be found to be less critical than synchronous signals. The differentiation offers circuit designers the ability to define the verification conditions for these types of signals independently.

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