Is it bad practice to use the positive/rising edge of a "non-clock" signal?

Question

Situation:

Before a data ready signal can go high it must wait for a data valid signal to go high. Once data ready goes high, data ready must remain high until a separate process is complete which should reset data ready to low and again data ready should wait for data valid to go high and so forth.

FPGA: xc7s25csga324-1, Spartan-7 S25, speed grade -1, Switching Characteristics

Timing diagram of hypothetical situation for a 3-bit sample:

Problem:

data valid only goes high for one clock cycle and so it would be convenient for the data ready to wait for the positive/rising edge of data valid.

Question:

Will programming the data ready signal to trigger on the positive/rising edge of data valid cause issues in implementation since data valid is not a clock?

Answer 1

If whatever you're interfacing to acts per the drawing, then AND data_ready and data_valid together, and sample at the falling edge of the clock. Then hold that state and do whatever you do with the incoming data bits until data_valid goes low, and stop.

Answer 2

Usually in a HDL implementation you want all register clocks (and by implication if rising_edge(xxx) and the like) to refer to actual clock signals. You can play it the other way, but it is not generally a great idea, mostly because it makes timing analysis hard.

Were I writing this, it would be a set reset latch set by data valid and reset once the three bits have been clocked in. The output from the SR latch is then data ready, and that is the only bit of asyncronous logic.

All the rest can be if rising_edge (clk) and data_ready then which will synthesise to clocked registers with clock enable inputs, which the timing analysis knows how to deal with.