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Situation:

Before a data ready signal can go high it must wait for a data valid signal to go high. Once data ready goes high, data ready must remain high until a separate process is complete which should reset data ready to low and again data ready should wait for data valid to go high and so forth.

FPGA: xc7s25csga324-1, Spartan-7 S25, speed grade -1, Switching Characteristics

Timing diagram of hypothetical situation for a 3-bit sample:

enter image description here

Problem:

data valid only goes high for one clock cycle and so it would be convenient for the data ready to wait for the positive/rising edge of data valid.

Question:

Will programming the data ready signal to trigger on the positive/rising edge of data valid cause issues in implementation since data valid is not a clock?

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    \$\begingroup\$ Draw the timing diagram please. \$\endgroup\$
    – Andy aka
    Commented Dec 3, 2021 at 18:53
  • \$\begingroup\$ in hobbyist electronic, you can have appoximative timings but it is always a risk to get a bad sequence each X% of use. Please give a real example and-or a datagram or time-diagram as example \$\endgroup\$
    – user201301
    Commented Dec 3, 2021 at 18:57
  • \$\begingroup\$ Does a usual D-flipflop with Reset (e.g. type 1G175) realize your function? If so, you have your answer. If the 175 is a real part that people use, its function is obviously not a "bad practise" \$\endgroup\$
    – tobalt
    Commented Dec 3, 2021 at 19:01
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    \$\begingroup\$ It is more convenient to sample datavalid as high on rising edge of clock. \$\endgroup\$
    – Mitu Raj
    Commented Dec 3, 2021 at 19:09
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    \$\begingroup\$ If your intention is to use data_ready as a back pressure signal, perhaps it would be better to redefine its meaning. Have a look at the AXI handshake for example, which places no restrictions on VALID and READY, and thus avoids a number of problems, including deadlock. All handshake state is computed prior to the rising edge of the clock, then sampled. \$\endgroup\$ Commented Dec 3, 2021 at 19:43

2 Answers 2

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If whatever you're interfacing to acts per the drawing, then AND data_ready and data_valid together, and sample at the falling edge of the clock. Then hold that state and do whatever you do with the incoming data bits until data_valid goes low, and stop.

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    \$\begingroup\$ That is an interesting idea! I'll try this and see what happens. \$\endgroup\$
    – Andrew
    Commented Dec 3, 2021 at 20:24
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Usually in a HDL implementation you want all register clocks (and by implication if rising_edge(xxx) and the like) to refer to actual clock signals. You can play it the other way, but it is not generally a great idea, mostly because it makes timing analysis hard.

Were I writing this, it would be a set reset latch set by data valid and reset once the three bits have been clocked in. The output from the SR latch is then data ready, and that is the only bit of asyncronous logic.

All the rest can be if rising_edge (clk) and data_ready then which will synthesise to clocked registers with clock enable inputs, which the timing analysis knows how to deal with.

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  • \$\begingroup\$ Thanks for the analysis. I ended up also implementing this using as an SR latch like you suggested and that has worked too \$\endgroup\$
    – Andrew
    Commented Dec 6, 2021 at 19:43

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