data ready signal can go high it must wait for a
data valid signal to go high. Once
data ready goes high,
data ready must remain high until a separate process is complete which should reset
data ready to low and again
data ready should wait for
data valid to go high and so forth.
FPGA: xc7s25csga324-1, Spartan-7 S25, speed grade -1, Switching Characteristics
Timing diagram of hypothetical situation for a 3-bit sample:
data valid only goes high for one clock cycle and so it would be convenient for the
data ready to wait for the positive/rising edge of
Will programming the
data ready signal to trigger on the positive/rising edge of
data valid cause issues in implementation since
data valid is not a clock?