# LTspice Half bridge inverter ringing and current spikes

I'm trying to build a pure sine wave inverter in LTspice but I'm having some trouble.

This is a test circuit, the voltage source outputs an SPWM signal which becomes a perfect sinewave after passing through the LC filter. Waveforms:

In this circuit, the SPWM source is replaced by 2 200VDC sources and a half-bridge. These are the MOSFETs used in this simulation: TK065U65Z

I would expect the output of the half-bridge to look like V(n001) from the previous circuit, but it doesn't at all. It oscillates between +200v and -200v throughout the whole period and zooming in shows some higher frequency (~111kHz) ringing. The filtered output doesn't look like the nice sinewave I was hoping for either.

Zoomed in on the ringing:

This is what the voltage across V3, the high-side MOSFET gate driver, looks like. V4 is the same but 180° out of phase.

Lastly, here's the current coming from the high-side MOSFET (red arrow on the circuit), which contains huge spikes.

My question is:

Why does the half-bridge output not look like the test circuit (why does it continuously oscillate between + and - 200V and why is it ringing)? And what can I do to fix it?

I'm thinking it has something to do with the first circuit actually pulling the output to 0V as opposed to the half-bridge just going high impedance.

#### These are the results of Andy's answer:

V3 and V4 output the same waveforms as the previous schematic.

• Please show us the parameters for V3, V4, and the MOSFETs. Commented Dec 4, 2021 at 1:26
• You are right that since the circuit isn't driving N003 straight to 0V, when the MOSFETs open, the voltage at that node will be determined by the circuit. What you really want is a "3-level PWM" half bridge (+200V, 0V, -200V) - google that. You will notice that people add more components to create a single pole, double throw switch (SPDT) - which is what you need for three levels in your circuit
– Big6
Commented Dec 4, 2021 at 4:51
• Maybe this will help? Otherwise I suspect you set zero valued trise and tfall in the voltage sources (and, if so, that will not achieve what you expect, because zero rise or fall time is a physical impossibility, and LTspice deals with that by setting 10% of min(Ton,T-Ton); there's no need to exaggerate, though, they can be set to about 100x...1000x smaller than T). Commented Dec 4, 2021 at 8:11
• @aconcernedcitizen Bookmarked the question, your answer contains some interesting points. Maybe replacing the mosfets with SWitches will solve the problem, but I want to build this in real life so I'll have to get it working (unless the mosfet model is flawed). V3 and V4 use a repeating PWL file that I generated with a Python script. Rise and fall times are 100ns, which seemed reasonable. Commented Dec 4, 2021 at 10:24
• @aconcernedcitizen Ohh, I didn't know you were talking about the schematic you sent. I thought you were talking about the "2nd schematic" in my question so I was confused and thought that you were telling me to change the triangle in my Python script. As for the SPWM generation, I used to do it with a comparator ("Image 1" in this question) but that was quite slow so I switched to using PWL. Your solution with a Schmitt gate is probably much faster than using a comparator and has the advantage of having everything in LTspice. Commented Dec 4, 2021 at 16:57

Why does the half-bridge output not look like the test circuit (why does it continuously oscillate between + and - 200V and why is it ringing)? And what can I do to fix it?

It's not a half bridge output; it's either the top transistor (one half cycle) or the bottom transistor (the other half cycle) that is active at any one time.

So, in the positive half cycle, you switch on the top MOSFET (U1) and current flows into the inductor. Then, due to PWM, you switch off U1 and get an almighty kick-back of energy from the inductor that pushes current back through the bulk diode in that MOSFET to the 200 volt supply rail.

So, you are not driving the circuit correctly. May I suggest that you establish the problem more directly using voltage controlled switches instead of MOSFETs and then you'll see the unholiest of back emfs because there won't be a bulk diode to catch it.

Maybe you should consider using a H-bridge type driver configuration like this (my drawing): -

• Hahah thanks, I'll give it a go with voltage controlled switches and add the results to my question. Commented Dec 4, 2021 at 10:25
• @Cecemel you don't need to do that; if the results are as I think they will be then it's a done deal regarding the problem. I think you need a proper H-bridge drive BTW hence, one pair on one side are PWMing whilst one MOSFET on the other side is high (or low) then, swap over for the next cycle as per the added image in my answer. Maybe simulate the circuit I've added. Commented Dec 4, 2021 at 10:29
• I wanted to use 3 of these on the same V+/V0/V- input rails for a three-phase inverter, with 0 being neutral. I don't think I can do that when using an H-bridge, right? Do you think adding a third mosfet to pull the output to V0, as Big6 suggested, would help? I suppose I'd need to use 2 of them in different polarity to block both positive and negative voltages.. I wonder how this is dealt with in commercial three-phase inverters. Commented Dec 4, 2021 at 10:39
• Sorry, but you are evolving the question before you have even established that my solution to the original question is correct. I'm quite happy to help with this but, please do things in the right order @Cecemel - given also that a 3 phase circuit is needed, I would certainly refrain from formally evolving this question; I'd get this problem resolved/understood then ask a brand new question. Maybe you should also take the 2 minute tour to understand my motivation here. Commented Dec 4, 2021 at 10:50
• Yes, understood, should've put that in my question from the start. I'll see if the H-bridge solves the problem and open a new question for three-phase. Commented Dec 4, 2021 at 11:11