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enter image description here

First, I would like to verify is the circuit I drawn correct? Rin is consider large enough to be negligible in the equation. enter image description here

I tried using KVL to obtain 3 equation as below, considering to get vth and Isc so Ro=vth/Isc $$-v_i+i(R_1+R_2+R_{out})+A_{vo}V_d=0$$ $$-v_i+iR_1-V_d=0$$ $$v_{th}=v_o=iR_0+A_{vo}V_d$$

and $$I_{sc}=\frac{v_i}{R_1+R_2}+\frac{AV_d}{R_{out}}$$ $$v_i=\frac{v_o}{A_{cl}}$$ where $$A_{cl}$$ mean close loop gain

I been substituting Vd in terms of i,R1 and Vi but the equation only become very complicated and I don't see anyway of getting the above equation. Is the equation I formed correctly? Also is there a much simpler method to get the output resistance?

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2 Answers 2

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It's probably better to use the dependent voltage source, as you did. But I'd infer it mentally and keep the schematic more like this:

schematic

simulate this circuit – Schematic created using CircuitLab

This allows me to quickly set up four equations and four unknowns. The purpose of \$I_{_\text{O}}\$ is to allow me to inject a current. I'd set it to \$0\:\text{A}\$ and then \$1\:\text{A}\$ and measure the difference of \$V_{_\text{O}}\$ (and divide by 1, the obvious change in current.)

Keeping all this in symbolic form can be handled easily with SymPy. So that's my recommendation.

Please note that in your paper-written diagram, you've not labeled the node between \$R_1\$ and \$R_2\$. I don't know if that's an oversight or if you are fully aware, but just didn't say anything about it. And I don't see how you can move towards the solution you show without it clearly named.

var( 'vi vo va ia r1 r2 rout vm avo io' )        # list needed variables
eq1 = Eq( vm/r1 + vm/r2, vi/r1 + vo/r2 )         # KCL for VM
eq2 = Eq( va, -avo*vm )                          # opamp open loop voltage gain
eq3 = Eq( vo/rout + vo/r2, va/rout + v/r2 + io ) # KCL for VO, with injection IO current
eq4 = Eq( va/rout, vo/rout + ia )                # KCL for VA, with opamp output current
ans = solve( [ eq1, eq2, eq3, eq4 ], [ v, ia, vo, va ] )
vo0 = ans[vo].subs( { io:0 } )                   # VO without injected current
vo1 = ans[vo].subs( { io:1 } )                   # VO with injected 1A current
pprint( simplify( vo1 - vo0 ) )                  # Print output resistance
     rout⋅(r₁ + r₂)
───────────────────────
avo⋅r₁ + r₁ + r₂ + rout

The above is exactly equivalent to your given correct answer. This can be tested in the following way:

n = rout*(r1+r2)/(r1+r2+rout)               # ROUT || (R1 + R2)
d = 1 + r1*avo/(rout+r1+r2)                 # 1 + R1*Avo/(ROUT + R1 + R2)
pprint( simplify( n / d ) )
     rout⋅(r₁ + r₂)
───────────────────────
avo⋅r₁ + r₁ + r₂ + rout

Their answer is correct and the approach shown above is soundly reasoned in getting to the same place.

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\$R_{out}= \dfrac{A_{OL}\cdot R_o}{A_{CL}} =\frac{R1}{R2}\cdot A_{OL}\cdot R_o,~ ~for ~I_o<< I_{max}\$ Which usually differs for positive and negative currents due to driver design differences.

This means Ro is reduced by the error correction of the feedback, which reduces the output impedance until it approaches the current limit then performs like a high impedance current-source with a soft knee transition.

So you can't measure Ro when the current limit is active as it raises Rout significantly.

Test Method

Measure % load "regulation error" without current limiting with a low voltage such as around 1mA to 10mA. This requires using a voltage near 0 for split supplies in both + and - voltages. For a single supply that would be relative to Vin+ near Vcc/2

Thus the way to test both polarities of Ro without current limiting is useful to for appreciating the difference of loading CMOS Op AMPs (generally high Ro with loads specified at 1k) vs BJT type Op Amps (generally current limited to 25 mA range). But there is a wide range of options with some over 1A that require heatsinks.

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