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I have a circuit where many NPN BJTs are interfacing 3.3 V GPIOs with higher voltage circuitry. Each application has a similar setup to the image below (resistor R422 is what's in question). I did this myself, but I am not sure where I got the idea to add resistors from the base to GND, and someone recently inquired about this and I couldn't give a good answer. Do these resistors serve a purpose?

As a side note, these transistors are being used for simple on/off purposes and are not on fast data transmission lines.

Circuit

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  • \$\begingroup\$ They may. Without them, parasitic stored charge may take a while to dissipate. It really depends on the situation, though, how badly you may want them. \$\endgroup\$
    – jonk
    Dec 6 '21 at 4:55
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    \$\begingroup\$ The BE resistor is mostly useful during MCU initialization when Pin state may not be defined and cause initial unwanted transistor ON state. It may be fatal in some applications like converters, switching high loads or unpleasant. \$\endgroup\$
    – user208862
    Dec 6 '21 at 5:10
  • \$\begingroup\$ Just a note on your comment: "As a side note these transistors are being used for simple on/off purposes and not for digital signals" You have described a digital signal here and then negated it. A digital signal is 0 (Off) or 1 (On). \$\endgroup\$
    – jwh20
    Dec 6 '21 at 17:49
  • \$\begingroup\$ @jwh20 I can edit the question, I meant this is not on a data transmission line. Like UART. \$\endgroup\$
    – Feynman137
    Dec 6 '21 at 18:36
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    \$\begingroup\$ @Feynman137 - Hi, Just FYI, useful search terms for transistors with that base-to-ground (actually base-to-emitter) resistor built-in include: "pre-biased transistors", "digital transistors" and "logic transistors" (some have both series-base and base-to-emitter resistors built-in, some only have one or the other). \$\endgroup\$
    – SamGibson ♦
    Dec 6 '21 at 23:52
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Depending on the MCU, its IO pin may be tri-state at power up (or reset) until it is programmed to either a '0' or a '1'. If it is tri-state, small amounts of leakage (on the transistor, pin, or PC board) may be amplified by the transistor and cause detrimental leakage on the collector.

When initialised, the IO pin will generate a good '0' or '1' and the resistor has negligible effect.

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  • \$\begingroup\$ Functionally, this has the effect that before the GPIO is initialized, RESET_N will be low (asserted) and hence at power up, everthing that is reset by RESET_N will be... reset. \$\endgroup\$
    – Rodney
    Dec 6 '21 at 14:41
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    \$\begingroup\$ @Rodney The OP said the circuits in question were "similar" to the given schematic, and I don't think we can assume that the RESET_N is to reset the same device that is supplying the GPIO_RESET. So, I don't think your comment is necessarily valid in this case. \$\endgroup\$
    – Elliot Alderson
    Dec 6 '21 at 20:52
  • \$\begingroup\$ @ElliotAlderson My comment applies to the diagram in the question, and to clarify, I am pointing out that, on power up, when GPIO_RESET is undriven, RESET_N will be asserted, which would be a sensible initial condition for it. No RESET_N will probably not reset the device that supplies GPIO_RESET that would not make sense and I didn't assume that or imply it. \$\endgroup\$
    – Rodney
    Dec 8 '21 at 9:58
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Not as commonly used as in MOSFET transistors, where you need a resistor from gate to GND to discharge the gate to source capacitance.

In a BJT, this is used to provide an alternative path to any leakage current or charge. Since a BJT will respond to even tiny currents through the base, it is possible to partially turn on a load with some GPIO leakage current (e.g. 50uA times a beta of 200 would mean a collector current of 10mA).

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  • \$\begingroup\$ Is it still possible to leak current/charge even if I have told my GPIO to be at GND voltage? \$\endgroup\$
    – Feynman137
    Dec 6 '21 at 5:03
  • \$\begingroup\$ @Feynman137 Yes. Because you have a resistor there. So the small capacitance at the BJT has to discharge through that resistor. It's not always a problem. Just sometimes. \$\endgroup\$
    – jonk
    Dec 6 '21 at 5:16
  • \$\begingroup\$ @Feynman137 If the GPIO is pulling low, it's pulling leakage to GND through R421 (1k). In this case, R422 (10k) does essentially nothing. \$\endgroup\$
    – John Doty
    Dec 6 '21 at 14:35
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    \$\begingroup\$ Yes if R422 was smaller than R421 it would improve the switch off time and / or deal with leakage but since it is 10x the size of R421 it's unlikely for that purpose. I agree with jp314 answer it is most likely there for when the gpio is undriven at power up. \$\endgroup\$
    – Rodney
    Dec 6 '21 at 14:38
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R422 is largely superfluous in normal operation except maybe when your MCU might be booting up or receives an unwanted reset due to EMI or code mistakes (god forbid!). When reset, some devices might default to having open-circuit IO lines and, this might cause semi-activation of those BJTs. It's not the same degree of problem if you were using a MOSFET because, a MOSFET's gate-source can charge up when presented with a high impedance and quite tiny leakage current.

You've just got to consider what might happen when the MCU is reset.

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