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The gain needs to be increased to 12, currently it is at 10 but I cannot seem to increase this any more. The circuit topology cannot change, but the component values can - except R4, the 56 kΩ resistor.

The input signal is 1 Vpk at 1 kHz. Therefore, I am hoping to achieve a +/- 12 V output. The supply of +/- 15 Vdc is fixed too. The load will be replaced by a class B push-pull amplifier. The quiescent DC voltage at the output should also be +2.4 Vdc.

I have tried to calculate the variables:

Vb = (Vout * R4) / (Vin-Vout) = (2.4 V * 56 k) / (30 V - 2.4 V) = 4869.57 Ω
VE = VB-VBE = 2.4 V-0.6 = 1.8 V
IC = IE = VE/RE = 1.8 V/1 k = 1.8 mA
VCQ = Vcc-IcRc = 30 V-(1.8 mA)(1 k) = 28.2 V

That is what I had tried. I had since had some help which led to the gain of 10, however, I cannot find how that was possible - nor how to increase further without clipping, hence my request for help.

enter image description here

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    \$\begingroup\$ We won't do your homework for you. You need to demonstrate that you have made a substantial effort to solve this yourself. Show us all of your work, then ask a specific question. \$\endgroup\$ Dec 6, 2021 at 20:46
  • \$\begingroup\$ Tom, what are the requirements? And why would you consider using a CE amplifier stage to drive a class-B? I'm asking for serious reasons. No one, not these days anyway, uses this particular CE stage. It's strictly for teaching BJTs and just about nothing else. There are so many better ways to go (bootstrapped CE, 2-BJT stages, etc.) Besides, it's much, much easier to use a diff-amp as the first stage because global NFB is almost trivially added (and it is definitely needed to deal with part vagaries.) So perhaps a little more discussion? \$\endgroup\$
    – jonk
    Dec 6, 2021 at 20:55
  • \$\begingroup\$ Steps how to do this: 1) Check the DC voltages and currents. 2) From the NPN's \$I_C\$ determine what the NPN's \$gm\$ will be. If you have no clue about \$gm\$, study: small signal analysis. 3) Draw the small signal equivalent circuit 4) determine an expression for the (voltage) gain. 5) look in the expression what decreases/increases the gain. But really, if you don't know what to do without all this then I think you first need to learn how this circuit actually works. How does it amplify a signal at the input? \$\endgroup\$ Dec 6, 2021 at 21:02
  • \$\begingroup\$ @ElliotAlderson Fair comment given the usual do your homework business here... I have added the theory I orignally applied. However, as I explain I did not find the results I hoped. The circuit was then altered by someone else but they could not tell me how they got the values, nor how to reach the x12 gain. \$\endgroup\$
    – Tom
    Dec 6, 2021 at 21:03
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    \$\begingroup\$ Keep R4 at 56k. Make R3=3k3, R1=15k. For gain of 12 and 30 V supply you don't need a partially by-passed emitter so remove R5 & C3 and connect R2 (1k) straight to negative supply. 56k & 3k3 base resistors bias base to about -13.3 V and so emitter is at -13.3-0.7 = -14 V which gives enough collector negative swing head room. Emitter voltage of 1 V across 1k gives collector current of 1 mA which flowing through 15 k collector resistor biases the collector to about 0 V. Gain equals (R6//R1)/(R2+re) where re=25mV/1mA. So gain is a little over 12 but it will vary with load impedance. \$\endgroup\$
    – James
    Dec 6, 2021 at 22:44

2 Answers 2

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Schematic

schematic

simulate this circuit – Schematic created using CircuitLab

Sanity Checks

Your output swing is \$\pm 12\:\text{V}\$ or \$24\:\text{V}_\text{PP}\$. Your power supply rails are \$\pm 15\:\text{V}\$ or \$30\:\text{V}\$. In addition, your emitter has to swing with the input, so that's \$\pm 1\:\text{V}\$ or \$2\:\text{V}_\text{PP}\$. Finally, \$Q_1\$ cannot be allowed to saturate. So there is a minimum collector-emitter voltage that must be reserved out. Not less than \$1\:\text{V}\$, as you don't know what the base-emitter voltage may be here.

So, accounting for all of the above, there's only \$3\:\text{V}\$ left over to work with. And that has to be used for the following items:

  1. You really do not want the collector current to go to zero. You can't drive the collector right up to the plus rail. So you absolutely must allow some voltage margin for the collector resistor.
  2. You really do want some voltage margin for \$R_{_{\text{E}_2}}\$ as this sets the quiescent current.
  3. The voltage across \$R_{_{\text{E}_1}}\$ cannot fall to zero (see #1 above) and will be about \$\frac1{\mid A_v\mid}\$ of whatever margin you reserve for #1, above. Or, put another way, #1 will be about \$\mid A_v\mid\$ times whatever you reserve here.

I think you can see why things are tight.

But looking at this, I'd say it is doable. If I set aside about \$500\:\text{mV}\$ for #2, then this means about \$200\:\text{mV}\$ minimum across \$R_{_{\text{E}_1}}\$. Sure, the \$2\:\text{V}_\text{PP}\$ rides on top of this and that means that there will be quite a %-variation of collector current and therefore some variation of voltage gain due to changes in \$r_e^{\,'}\$ (which is also affected by temperature.) But it is livable.

So it passes the basic sanity check.

That said, I'd like to see \$C_{_\text{E}}\$ set very large, so as to keep variations of the voltage across \$R_{_{\text{E}_2}}\$ from causing trouble, given how tight things are. A few millivolts of variation are tolerable here. But things are very tight. So getting sloppy is a recipe for trouble. Making \$C_{_\text{E}}\$ large mitigates this worry of mine.

Design

I'm going to set off \$500\:\text{mV}\$ for \$R_{_{\text{E}_2}}\$, so there's only \$2.5\:\text{V}\$ left now for \$R_{_\text{C}}\$'s minimum voltage margin plus the minimum voltage margin for \$R_{_{\text{E}_1}}\$. Since those are related to each other by the voltage gain, \$A_v\$, it's all in a single package. Without accounting for \$r_e^{\,'}\$ in this mess, this means \$\frac{2.5\:\text{V}}{\mid A_v\mid +1}\approx 190\:\text{mV}\$ for \$R_{_{\text{E}_1}}\$'s minimum and about \$2.31\:\text{V}\$ for \$R_{_{\text{C}}}\$'s minimum.

From this, I find:

$$\begin{align*} V_{_{\text{C}_\text{Q}}}&=+15\:\text{V}-2.31\:\text{V}-12\:\text{V}&=690\:\text{mV} \\\\ V_{_{\text{E}_\text{Q}}}&=-15\:\text{V}+500\:\text{mV}+190\:\text{mV}+1\:\text{V}&=-13.31\:\text{V} \end{align*}$$

There's no quiescent current specification, no THD specification, no temperature stability specification, etc... so I can pretty much pick any quiescent current I want.

Standard values for resistors may be a problem if you are supposed to nail the voltage gain, exactly. But I suspect that's not a problem. (It better not be, because BJTs vary a lot, temperature varies, and this stage is going to have a varying voltage gain anyway because of the very wide swings and practically no voltage margins to work with.) So we can get close to the right voltage gain and just be happy.

So let's just pick \$R_{_{\text{C}}}=4.7\:\text{k}\Omega\$ as a starting point. (Have to start somewhere.) Since we need to drop a quiescent \$2.31\:\text{V}+12\:\text{V}=14.31\:\text{V}\$, we find \$I_{_{\text{C}_\text{Q}}}=\frac{14.31\:\text{V}}{4.7\:\text{k}\Omega}\approx 3\:\text{mA}\$.

I don't know what the BJT \$\beta\$ is (the emitter current will be slightly more), but we can estimate \$R_{_{\text{E}_1}}=\frac{190\:\text{mV}+1\:\text{V}}{3\:\text{mA}}\approx 390\:\Omega\$. Convenient.

And now \$R_{_{\text{E}_2}}=\frac{500\:\text{mV}}{3\:\text{mA}}\approx 165\:\Omega\$. We need to pick something standard. Either way, this will mess with the reserved \$500\:\text{mV}\$. But that's okay. Because things are so tight, let's use a smaller resistor value here, \$R_{_{\text{E}_2}}=150\:\Omega\$, and recalculate that we'll drop about \$450\:\text{mV}\$, plus a little because the emitter current is a little higher. Call it \$460\:\text{mV}\$.

Guessing about \$700\:\text{mV}\$ for the base-emitter voltage, this means the base voltage for \$Q_1\$ is \$-15\:\text{V}+460\:\text{mV}+1.19\:\text{V}+700\:\text{mV}=-12.65\:\text{V}\$.

A stiff divider will have about 10% of the collector current, or \$300\:\mu\text{A}\$, in \$R_{_{\text{B}_2}}\$. So \$R_{_{\text{B}_2}}=\frac{-12.65\:\text{V}-\left(-15\:\text{V}\right)}{300\:\mu\text{A}}\approx 7.83\:\text{k}\Omega\$. Since you have a low-impedance signal generator driving this, I'm going to round the resistor value down to \$R_{_{\text{B}_2}}=7.5\:\text{k}\Omega\$ and re-calculate \$\frac{-12.65\:\text{V}-\left(-15\:\text{V}\right)}{7.5\:\text{k}\Omega}\approx 313\:\mu\text{A}\$ as the current.

Since the base current will be no worse than \$\frac1{100}\$th of the collector current, the required current for \$R_{_{\text{B}_1}}\$ is \$313\:\mu\text{A}+30\:\mu\text{A}=343\:\mu\text{A}\$. So \$R_{_{\text{B}_1}}=\frac{15\:\text{V}-\left(-12.65\:\text{V}\right)}{343\:\mu\text{A}}\approx 80.6\:\text{k}\Omega\$. Also not a standard value. Since we know the base current might be (probably is) less than estimated, we can raise the value so that \$R_{_{\text{B}_1}}=82\:\text{k}\Omega\$.

The final circuit is:

schematic

simulate this circuit

Now, I honestly have no idea if I've made some gross mistake above, except to try it out in LTspice. Hopefully, it either will confirm my hopes or else it will help me find a mistake in my above work product.

Also, all of the above adjustments to find standard resistor values have also changed some of my earlier assumptions. And it is tight in here. Real tight. There's not a lot of wiggle room for adjustments. So even if I got things right, when you build this thing I'd still expect the need for some minor, final tweaks to deal with vagaries of BJTs and resistor tolerances and the ambient temperature. There just is NOT enough headroom in order to make a design that is bullet-proof against temperature and part variations. Can't be done with so little headroom.

My last caveat is that I expect the voltage gain to be a little below expectations because I didn't account for \$r_e^{\,'}\$, which is about \$9\:\Omega\$. If you find that the gain isn't to your liking, feel free to lower the value of \$R_{_{\text{E}_1}}\$ by about that much.

Let's see.

enter image description here

Looks like \$\mid A_v\!\mid\, \approx 11\$. Close. Plus, it worked without exhibiting any clipping. And it did this without me making any gross mistakes, either. Kind of "just worked."

You can set the emitter capacitor back to a smaller value, if you want. That will allow a larger swing there. But the ripple was only a couple of millivolts (I checked) with that large capacitor I used. Putting it back to your value will mean maybe \$80\:\text{mV}\$ of peak to peak ripple. But I don't think anyone will care that much about the consequences of it. The output will still look okay on a scope.

When you get to building one of these, just get things up and see what you have. Check the collector voltage signal, directly. If it is clipping on the bottom then you are saturating the BJT (pushing up against the emitter too tightly) and you can open things up a bit by increasing the value of \$R_{_{\text{E}_2}}\$ (because that will lower the quiescent current.) If things are clipping on the top, then do the opposite. You can use this resistor to move your collector curve up or down, that way. (Please note that I'm not talking about the output across the \$100\:\text{k}\Omega\$ load resistor. I'm actually talking about the signal variations at the collector of \$Q_1\$. Keep that straight!)

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    \$\begingroup\$ Thank you so much for the help! It’s really appreciated that you’ve done so much. This has really given me some extra understanding of the circuit, which I have not been as clear previously \$\endgroup\$
    – Tom
    Dec 7, 2021 at 11:21
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    \$\begingroup\$ @Tom You interacted well, here, which suggests you want to know more. That's a good and worthy trait. And thanks very much for letting me know it helped. Makes it all worth the time! Best wishes and be sure to help others when you find a moment and someone else interested. Pass it on. \$\endgroup\$
    – jonk
    Dec 7, 2021 at 14:27
  • \$\begingroup\$ Guessing about 700mV for the base-emitter voltage, this means the base voltage for 𝑄1 is −15V+460mV+1.19V+700mV=−12.65V. - Please can you clarify where the 1.19V has come from? Maybe it is very simple, but I should ask rather than guess. \$\endgroup\$
    – Tom
    Dec 7, 2021 at 14:53
  • \$\begingroup\$ @Tom It comes from the 190 mV minimum plus the 1 V peak signal value. The emitter resistor (1) will go from 190 mV across it to 2.190 V across it. The quiescent point is halfway between the two. \$\endgroup\$
    – jonk
    Dec 7, 2021 at 14:58
  • \$\begingroup\$ Thank you very much. I understand that now. Again, much appreciated! \$\endgroup\$
    – Tom
    Dec 7, 2021 at 14:59
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How to increase CE amplifier gain to 12 in five steps

First, identify essential components of your design and make sure you understand their purpose.

  1. NPN transistor. This is an amplifying device.
  2. Resistor R1 connecting the transistor collector to VCC. The transistor operates as the current/voltage controlled current source, the resistor transforms the current generated to an output voltage.
  3. Two resistors and a capacitor connecting the emitter to VEE. The prototypical CE requires no such components as the emitter is connected to the network common for both input and output ports.
  4. The input signal source and network (a signal voltage source, a coupling capacitor, voltage divider resistors).
  5. The output RC network.

First, look at the CE with the degeneration resistor in its emitter network.

CEwithRE

With the input voltage in the range falling between -14.4V and -11.65V, the transistor operates in the active mode. The slope of the voltage transfer characteristic is (15 - (-12.16))/(-14.45 - (-11.65)) = -9.7 and depends on the transistor beta (in the range of 60<BF<630) only weakly.

This resistor solves the problems of variability of transistor parameters and of dependence on temperature and biasing. In particular, the transistor transconductance \$g_m\$ depends on biasing, but with this resistor added the voltage gain is

$$ {{-g_mR_C} \over {g_mR_E+1}} \sim -{R_C \over R_E} \tag{A_V} $$

independent of \$g_m\$, and this equation gives the condition \$g_mR_E \gg 1\$ that enables us to make the voltage gain independent of biasing. The equation \$A_V \sim -R_C/R_E\$ explains the figure -9.7 for the VTC slope of the above CE, close to -12K/1.2K = -10.

If you are insecure with this explanation, examine the CE circuit with the transistor substituted by its Ebers Moll model. The value AF = BF/(1+BF) is the ratio of the collector and emitter currents and appears in this circuit as the factor 292.4/(1 + 292.4) of the controlled current source parameter, 292.4 is BF of the BC337-25 model

EMofCEwithRe

Having identified the role of the degeneration resistor and its contribution to the total voltage gain, we make the first correction of the component values in your circuit: the total resistance in the emitter network is now 1.2K, one tenth of the collector resistance. Why one tenth and not one twelfth, as our target is \$A_V=12\$ and the equation A_V gives \$R_E = R_C/A_V\$? Here, only to demonstrate the purpose of the bypassed resistor R5 in your circuit, although there exist designs where bypassed degeneration resistors solve real problems.

VoltageDivider56_20

In the voltage ranges (0-0.5)mV, (1-1.5)mV, (2-2.5)mV, etc. the base current peaks up to 1mA and the transistor enters the saturation mode. The reason is clear, the biasing voltage divider R4/R3 sets too high a bias voltage, and it must be decreased by decreasing the R3 value. The math gives the value of approx. 4K that guarantees that the collector voltage is always greater than the emitter voltage. To be on the safe side and previewing the total voltage gain increase in the next step, select the value of 3.3K for R3. Do not be confused by seemingly coarse considerations when selecting the component values: when developing with simulator, you can always step back and modify the component values.

VoltageDivider56_3.6

Now, right to our goal of 12 fold amplification factor. We separate the degeneration resistor into two components, R2 and R5, so that their total resistance amounts to 1.2K. Equal partitioning into 620/620 greatly enhances the total gain and the transistor again enters saturation within the (0-0.5)mV, (1-1.5)mV, (2-2.5)mV, etc. input voltage ranges. Lowering the bypassed part to 430 Ohm gives the output swing from -12.59V to +12.23V. To be on the safe side, we select the 910/330 ratio.

PartiallyBypassedCE

The problem is solved, although the design seems to have only instructional value: it is easy to see by inspection how much the signal is distorted, although not being outright clipped. Notice that only necessary modifications are made to your design: only R2, R3 and R5 resistor values are changed. Well, I've also increased the R6 value to 1MEG, only to simplify the calculation by having the current through R1 almost equal to the current through R2. You can change this value back to 100K, this changes the voltage gain only insignificantly.

Another question might arise, is it necessary to change the bypass capacitor C3 value? The AC analysis indicates that there no need to do this.

PartiallyBypassedCE

To get more of that exercise, you can try a corner analysis for this design, varying BF (DC current gain) and VAF (Early voltage) parameters. This is the point of substituting a one-off BC337-CC model (.model BC337-CC AKO:BC337-25 BF=292.4 VAF=145.7) with easily accessible parameters BF and VAF, instead of the library BC337-25 model.

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