Sample and Hold -- Lower Voltage Ignoring Sample Signal

Question

I've built the following sample-and-hold circuit on a breadboard:

When I input a larger voltage than is currently stored across C1, the circuit works perfectly; it waits for the Sample signal, at which point it charges C1 to the input voltage. However, when the input voltage is lower than C1, the capacitor discharges immediately, ignoring the prompt of the Sample signal.

After some discussion with some senior circuit designers, it seems to me that the MOSFET's body diode is being forward biased when the input voltage is lower than the voltage across C1, allowing it to discharge through R1 immediately regardless of the state of the Sample signal.

I'm brainstorming some ways to circumvent this problem, but I'm not coming up with anything. A Google search suggests that the body diode is intrinsic to MOSFETs, so it's not viable to find just another part number. I also considered throwing another diode into the circuit, but I can't think of a way to do that without preventing the op-amp from sinking current entirely, which it does need to be able to do upon receiving the Sample signal.

Does anyone have any ideas as to what to do?

Answer 1

Use two FETs back-to back (sources connected together; gates connected together to SAMPLE.) This will counter the effect of the body diode.

You could also use a 4-terminal FET with a separate body connection.

More about all that here: Two directional FET switch. Is it possible?

One other issue you might have is that the SAMPLE signal needs to be driven high enough to get the entire positive signal range: at least one Vgs threshold higher. If you use p-FETs you won’t have this problem.