A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency.
The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 Hz and a maximum of around 5 kHz.
As the multiplier is 12000, the output master clock's central frequency is 12 MHz. The master clock will range between 0 Hz and 60 MHz. The output master clock can be tonal or rectangular. However a tone is preferred.
Is there a modern way to generate such a master clock from a low frequency reference tone ? Is it possible to meet a latency which is or the order of microseconds ? Is it possible to have very low jitter ?
NOTE: This question is similar to the VCO+PLL question, however this questions asks for a DDS based solution.