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What is the purpose of capacitor C4 (47 pF) in this circuit?

Datasheet

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    \$\begingroup\$ Improving stability. \$\endgroup\$ Dec 7, 2021 at 13:48
  • \$\begingroup\$ I would say it's a feedback signal filtering. \$\endgroup\$
    – user208862
    Dec 7, 2021 at 14:07
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    \$\begingroup\$ A warm welcome to the site. You have already asked a question on this regulator circuit of yours (electronics.stackexchange.com/questions/598224/dc-dc-converter). Please do not get into the habit of asking a quick series of questions about the same thing. It's a Q&A site, not a discussion forum or online technical helpdesk for personal tutorial. You'll get better results asking a larger, well-written question that covers all of your topics. Thanks and, again, welcome. \$\endgroup\$
    – TonyM
    Dec 7, 2021 at 14:29
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    \$\begingroup\$ I'm a moderator: TonyM's advice is a statement of site policy and is covered in the site rules/guidelines. You'll find it helpful to yourself and others to keep your questions on a specific point within the same question, as asking similar questions in multiple efforts both dilutes the answers received and makes the Q&A less useful to others in the longer term. \$\endgroup\$
    – Russell McMahon
    Dec 8, 2021 at 10:04
  • \$\begingroup\$ As well as the other comments you have received you can consider C4 intuitively as providing rapid response to transient load changes. A step or sharp change at the output is conducted by C4 as a high frequency pulse directly to the feedback pin allowing rapid initial response. \$\endgroup\$
    – Russell McMahon
    Dec 8, 2021 at 10:06

3 Answers 3

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The trouble with converters like this is that they can go unstable quite easily and need a hand to prevent this from happening. Unlike linear voltage regulators, the feedback isn't directly from the chip output but, passes via an LC low-pass filter. Of course, that LC filter is needed (for switching regulators) to give a fairly decent DC voltage at the output but, consider what happens both below and above the cut-off frequency of the LC low-pass filter: -

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Image from my crappy website. Don't feel pressurized or inclined to go there at all because all you need to know is pictured above. The green trace is phase angle shift.

A bit below the cut-off frequency, \$F_n\$ (~9.2 kHz with the component values from the question), the phase angle of the filter's output signal will be close to 0°. That's not a problem and also, it's pretty much what a linear regulator will receive at its FB terminal. But, above 9.2 kHz there will be a near 180° phase shift before 40 kHz is reached. That represents a big problem if not handled correctly. Any extra degree or two of phase shift will turn a simple buck regulator into an oscillator (due to the phase of the FB signal becoming inverted).

So, if you add a small value capacitor across the top feedback resistor you can retard the lagging phase of the fed-back signal from nearly 180° to something more like 150° and, at much higher frequencies, it will retard the phase back to about 90°.

$$\color{red}{\text{This stops the circuit becoming an unwanted chip-busting oscillator}}$$

Sometimes things won't go unstable but, one little transient load condition change on the output can make these devices sing out loud.

Think about a linear voltage regulator; if instead of taking the feedback directly from the output, you inserted an inductor between output and smoothing capacitor, would you really expect decent performance and no load-induced crazy overshoots on the output voltage and, no oscillations?

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As it is mentioned on page 17 of the AP63300 datasheet "An optional external capacitor, C4 in Figure 1, of 10pF to 220pF improves the transient response."

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Maintaining AC loop stability in a DCDC can be complex, although since this AP63300 uses a current-mode controller, it is a little easier. However it is still important to avoid adding unwanted responses (especially additional poles) to the loop frequency response.

The feedback resistor divider is relatively high impedance, and assuming a reasonable value of 10 pF for parasitic capacitance on the FB pin (from the IC's pin capacitance, also the PCB), there would be a pole at 10p*(158k//30k), or 630 kHz. The 47 pF cancels this pole -- in effect by bypassing the 158k resistor. Basically, above 'medium' frequencies (above 47p*158k == 21 kHz) it adds phase to the feedback loop. This can help loop stability and minimize the effect of non-idealities inside the IC's controller (such as delay in the current sensing circuit, or PWM comparator).

In addition to perhaps help maintain loop stability, by increasing the loop bandwidth (i.e. keeping loop gain high until higher frequencies), this also improves load transient response -- the loop can respond 'quicker'.

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